R5F21133DFP RENESAS [Renesas Technology Corp], R5F21133DFP Datasheet - Page 132

• Manufacturer Part Number: R5F21133DFP
• Description: 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY/R8C/Tiny SERIES
• Manufacturer: RENESAS [Renesas Technology Corp]

R8C/13 Group
Rev.1.20
REJ09B0111-0120
Figure 13.9 Transmit Operation
• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
• Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)
The above timing diagram applies to the case where the register
bits are set as follows:
Transfer clock
UiC1 register
TI bit
TxDi
Transfer clock
TxDi
UiC1 register
TE bit
UiC0 register
TXEPT bit
SiTIC register
IR bit
UiC1 register
TE bit
UiC1 register
TI bit
UiC0 register
TXEPT bit
SiRIC register
IR bit
The above timing diagram applies to the case where the register bits
are set as follows:
• UiMR register PRYE bit = 0 (parity disabled)
• UiMR register STPS bit = 1 (2 stop bits)
• UiIRS bit = 0 (an interrupt request occurs when transmit buffer
• UiMR register PRYE bit = 1 (parity enabled)
• UiMR register STPS bit = 0 (1 stop bit)
• UiIRS bit = 1 (an interrupt request occurs when transmit completed):
Jan 27, 2006
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
becomes empty)
page 121 of 205
Start
bit
ST
Start
ST
bit
D
D
Write data to UiTB register
0
Set to “0” when interrupt request is accepted, or set by a program
0
Write data to UiTB register
D
D
1
1
Tc
D
D
2
2
D
D
3
3
Tc
D
D
4
4
Transferred from UiTB register to UARTi transmit register
D
D
5
5
D
D
6
6
D
D
7
7
Parity
D
bit
P
8
Stop
bit
SP
SP
Stop
bit
SP
Set to “0” when interrupt request is accepted, or set by a program
Stop
bit
Tc = 16 (n + 1) / fj or 16 (n + 1) / f
i: 0, 1
ST
Tc = 16 (n + 1) / fj or 16 (n + 1) / f
i: 0, 1
ST
13.2 Clock Asynchronous Serial I/O (UART) Mode
D
Transferred from UiTB register to UARTi
transmit register
fj: frequency of UiBRG count source (f
f
n: value set to UiBRG
0
EXT
fj: frequency of UiBRG count source (f
f
n: value set to UiBRG
EXT
D
D
0
1
: frequency of UiBRG count source (external clock)
: frequency of UiBRG count source (external clock)
D
D
1
2
D
D
2
3
D
D
3
4
D
D
4
5
D
D
5
6
D
D
6
EXT
7
EXT
D
7
P SP
Stopped pulsing
because the TE bit
= “0”
D
8
SPSP
1SIO
1SIO
, f
, f
8SIO
8SIO
ST
ST
, f
, f
D
32SIO
D
0
32SIO
0
D
D
1
)
1
)