R5F21133DFP RENESAS [Renesas Technology Corp], R5F21133DFP Datasheet - Page 66

• Manufacturer Part Number: R5F21133DFP
• Description: 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY/R8C/Tiny SERIES
• Manufacturer: RENESAS [Renesas Technology Corp]

R8C/13 Group
Rev.1.20
REJ09B0111-0120
Figure 10.4 Time Required for Executing Interrupt Sequence
Address bus
CPU clock
Data bus
• Interrupt Sequence
(1) The CPU gets interrupt information (interrupt number and interrupt request priority level) by read-
(2) The FLG register immediately before entering the interrupt sequence is saved to the CPU internal
(3) The I, D and U flags in the FLG register become as follows:
(4) The CPU’s internal temporary register
(5) The PC is saved to the stack.
(6) The interrupt priority level of the accepted interrupt is set in the IPL.
(7) The start address of the relevant interrupt routine set in the interrupt vector is stored in the PC.
After the interrupt sequence is completed, the processor resumes executing instructions from the start
address of the interrupt routine.
NOTES:
Jan 27, 2006
An interrupt sequence — what are performed over a period from the instant an interrupt is accepted
to the instant the interrupt routine is executed — is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when
the execution of the instruction is completed, and transfers control to the interrupt sequence from the
next cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA
instruction, the processor temporarily suspends the instruction being executed, and transfers control
to the interrupt sequence.
The CPU behavior during the interrupt sequence is described below. Figure 10.4 shows time re-
quired for executing the interrupt sequence.
1. This register cannot be used by user.
The indeterminate state depends on the instruction queue buffer. A read cycle occurs when the instruction queue buffer is ready
to accept instructions.
WR
RD
The I flag is cleared to “0” (interrupts disabled).
The D flag is cleared to “0” (single-step interrupt disabled).
The U flag is cleared to “0” (ISP selected).
However, the U flag does not change state if an INT instruction for software interrupt numbers 32 to
63 is executed.
ing the address 00000
not requested).
temporary register
1
Address
0000
2
information
page 55 of 205
Interrupt
16
3
(1)
4
.
16
Indeterminate
5
Indeterminate
. Then it clears the IR bit for the corresponding interrupt to “0” (interrupt
Indeterminate
6
7
8
(1)
SP-2
is saved to the stack.
contents
9
SP-2
SP-1
contents
10
SP-1
SP-4
contents
11
SP-4
12
SP-3
contents
SP-3
13
VEC
contents
14
VEC
15
VEC+1
contents
VEC+1
16
10.1 Interrupt Overview
VEC+2
17
contents
VEC+2
18
19
PC
20