MCF5207 FREESCALE [Freescale Semiconductor, Inc], MCF5207 Datasheet - Page 31

• Manufacturer Part Number: MCF5207
• Description: Microprocessor Data Sheet
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

NOTES:
1
2
3
4
5
6
7
8
9
DD10
DD11
DD12
DD13
DD14
DD15
Command output valid should be 1/2 the memory bus clock (SD_CLK) plus some minor adjustments for process, temperature, and
voltage variations.
Num
The frequency of operation is either 2x or 4x the FB_CLK frequency of operation. FlexBus and SDRAM clock operate at the same
frequency as the internal bus clock.
SD_CLK is one SDRAM clock in (ns).
Pulse width high plus pulse width low cannot exceed min and max clock period.
This specification relates to the required input setup time of today’s DDR memories. The device’s output setup should be larger
than the input setup of the DDR memories. If it is not larger, then the input setup on the memory will be in violation.
MEM_DATA[31:24] is relative to MEM_DQS[3], MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to
MEM_DQS[1], and MEM_[7:0] is relative MEM_DQS[0].
The first data beat will be valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats will
be valid for each subsequent DQS edge.
This specification relates to the required hold time of today’s DDR memories. MEM_DATA[31:24] is relative to MEM_DQS[3],
MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to MEM_DQS[1], and MEM_[7:0] is relative
MEM_DQS[0].
Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line becomes
valid. This input skew must include DDR memory output skew and system level board skew (due to routing or other factors).
Data input hold is derived from each DQS clock edge. It begins with a DQS transition and ends when the first data line becomes
invalid.
Freescale Semiconductor
DD5
DD6
DD7
DD8
DD9
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_CS[1:0] - Output Hold
Write Command to first DQS Latching Transition
Data and Data Mask Output Setup (DQ-->DQS)
Relative to DQS (DDR Write Mode)
Data and Data Mask Output Hold (DQS-->DQ)
Relative to DQS (DDR Write Mode)
Input Data Skew Relative to DQS (Input Setup)
Input Data Hold Relative to DQS.
DQS falling edge from SDCLK rising (output hold time)
DQS input read preamble width (t
DQS input read postamble width (t
DQS output write preamble width (t
DQS output write postamble width (t
Characteristic
MCF5208 ColdFire
Table 11. DDR Timing Specifications (continued)
RPRE
RPST
WPRE
WPST
)
)
)
)
®
Microprocessor Data Sheet, Rev. 0.5
Preliminary
t
t
t
t
t
Symbol
DQLSDCH
t
t
SDCHACI
CMDVDQ
t
DQWPRE
DQWPST
DQRPRE
t
DQRPST
DQDMV
t
DQDMI
t
DVDQ
DIDQ
0.25 × SD_CLK
+ 0.5ns
0.25
Min
2.0
1.5
1.0
0.5
0.9
0.4
0.4
—
Preliminary Electrical Characteristics
Max
1.25
1.1
0.6
0.6
—
—
—
—
—
—
1
SD_CLK
SD_CLK
SD_CLK
SD_CLK
SD_CLK
Unit
ns
ns
ns
ns
ns
ns
Notes
31
5
6
7
8
9