MCF5207 FREESCALE [Freescale Semiconductor, Inc], MCF5207 Datasheet - Page 44

• Manufacturer Part Number: MCF5207
• Description: Microprocessor Data Sheet
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Revision History
44
Revision
Number
0.2
0.3
0.4
0.5
10/10/2005
8/26/2005
9/07/2005
3/29/2006
Date
MCF5208 ColdFire
Table 24. Revision History (continued)
Cleaned up various electrical specifications:
• Changed ball M9 from SD_VDD to EVDD in
•
•
•
•
• Added filtering circuits and voltage sequencing sections:
• Removed “Operating Conditions” table from
•
• Corrected DRAMSEL footnote #3 in
• Updated
• Added 144MAPBGA ballmap to
• Changed J12 from PLL_VDD to IVDD in
•
•
•
• Added “top view” and “bottom view” labels where appropriate to
• Updated mechanical drawings to latest available, and added note to
Table
SD_VDD. BE/BWE[3:0] for 144 LQFP should be “20, 48, 18, 50“ instead
of “18, 20, 48, 50”
Table
synthesizer supply voltage” to “PLL supply voltage”, changed min PLLV
from -0.5 to -0.3, changed max V
from -65 to -55,
Table
Table
maximum from 1.65 to 1.6, added PLL supply voltage entry, added pad
supply entries for mobile-DDR, DDR, and SDR, changed minimum input
high voltage from 0.7xEV
changed minimum input low voltage from VSS-0.3 to -0.05 and maximum
from 0.35xEV
mobile-DDR, removed high impedance leakage current entry, changed
minimum output high voltage from EV
output high/low voltage entries, removed load capacitance and DC
injection current entries.
“PLL Power Filtering,”
Separation Cautions.”
PLL Electrical Characteristics,”
Table
reference and on-chip PLL frequency specs to have only a CLKOUT
frequency spec of TBD to 83.33MHz, removed loss of reference frequency
and self-clocked mode frequency entries, in EXTAL input high/low voltage
entries changed “All other modes (Dual controller (1:1), Bypass, External)”
to “All other modes (External, Limp)”, removed XTAL output high/low
voltage entries, removed power-up to lock time entry, removed last 5
entries (frequency un-lock range, frequency lock range, CLKOUT period
jitter, frequency modulation range limit, and ICO frequency)
Figure 1
Figure 4
Figure 6
from TEST to VSS
mechanical drawings and pinouts.
Section 4, “Mechanicals and Pinouts.”
®
Microprocessor Data Sheet, Rev. 0.5
3: Pin 33 for 144 LQFP package should be EVDD instead of
4: Added DDR/Memory pad supply voltage spec, changed “clock
5: Changed TBD values in T
7: Changed minimum core supply voltage from 1.35 to 1.4 and
9: Changed minimum core frequency to TBD, removed external
Preliminary
and
and
and
Table 3
Table
Table
Table
DD
to 0.8, added input high/low voltage entries for DDR and
with 144MAPBGA pin locations.
3: Changed pin 39 from EVDD to SD_VDD and pin 117
3: Changed pin 33 from EVDD to SD_VDD
3: Changed ball D10 from TEST to VSS
and
Substantive Changes
DD
Section 5.4.2, “Supply Voltage Sequencing and
to 2 and maximum from 3.65 to EV
since it is redundant with
IN
Section 4.3, “Pinout—144 MAPBGA.”
j
from 4.0 to 3.6, changed minimum T
entry to 105°C.
Table
DD
-0.5 to EV
Figure
3.
Section 5.5, “Oscillator and
Figure
9.
DD
9.
-0.4, added DDR/bus
Freescale Semiconductor
Table
Section 5.4.1,
7.
DD
+0.05,
DD
stg