MCF5329DS ANALOGICTECH [Advanced Analogic Technologies], MCF5329DS Datasheet - Page 28

• Manufacturer Part Number: MCF5329DS
• Description: MCF5329 ColdFire Microprocessor Data Sheet
• Manufacturer: ANALOGICTECH [Advanced Analogic Technologies]

NOTES:
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Preliminary Electrical Characteristics
5.8.2
When using the SDRAM controller in DDR mode, the following timing numbers must be followed to
properly latch or drive data onto the memory bus. All timing numbers are relative to the four DQS byte
lanes. The following timing numbers are subject to change at anytime, and are only provided to aid in early
board design. Please contact your local Freescale representative if questions develop.
28
DD10 Input Data Hold Relative to DQS.
DD11 DQS falling edge from SDCLK rising (output hold time) t
DD12 DQS input read preamble width
DD13 DQS input read postamble width
DD14 DQS output write preamble width
DD15 DQS output write postamble width
Num
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
The frequency of operation is either 2x or 4x the FB_CLK frequency of operation. FlexBus and SDRAM clock operate at the
same frequency as the internal bus clock.
SD_CLK is one SDRAM clock in (ns).
Pulse width high plus pulse width low cannot exceed min and max clock period.
Command output valid should be 1/2 the memory bus clock (SD_CLK) plus some minor adjustments for process,
temperature, and voltage variations.
This specification relates to the required input setup time of today’s DDR memories. Rigoletto’s output setup should be larger
than the input setup of the DDR memories. If it is not larger, then the input setup on the memory will be in violation.
MEM_DATA[31:24] is relative to MEM_DQS[3], MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to
MEM_DQS[1], and MEM_[7:0] is relative MEM_DQS[0].
The first data beat will be valid before the first rising edge of DQS and after the DQS write preamble. The remaining data
beats will be valid for each subsequent DQS edge.
This specification relates to the required hold time of today’s DDR memories. MEM_DATA[31:24] is relative to MEM_DQS[3],
MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to MEM_DQS[1], and MEM_[7:0] is relative
MEM_DQS[0].
Frequency of Operation
Clock Period
Pulse Width High
Pulse Width Low
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_CS[1:0] - Output Valid
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_CS[1:0] - Output Hold
Write Command to first DQS Latching Transition
Data and Data Mask Output Setup (DQ-->DQS)
Relative to DQS (DDR Write Mode)
Data and Data Mask Output Hold (DQS-->DQ)
Relative to DQS (DDR Write Mode)
Input Data Skew Relative to DQS (Input Setup)
DDR SDRAM AC Timing Characteristics
Characteristic
MCF5329 ColdFire
Table 12. DDR Timing Specifications
®
Microprocessor Data Sheet, Rev. 0.1
Preliminary
t
t
t
t
t
Symbol
SDCHACV
DQLSDCH
t
t
SDCHACI
CMDVDQ
t
DQWPRE
DQWPST
t
DQRPRE
t
t
DQRPST
DQDMV
t
DDCKH
t
DDCKL
t
DQDMI
t
DDCK
DDSK
DVDQ
DIDQ
0.25 × SD_CLK
+ 0.5ns
TBD
0.45
0.45
0.25
Min
2.0
1.5
1.0
0.5
0.9
0.4
0.4
80
—
—
—
0.5 × SD_CLK
+ 1.0
Max
TBD
12.5
0.55
0.55
1.25
1.1
0.6
0.6
—
—
—
—
—
1
Freescale Semiconductor
SD_CLK
SD_CLK
SD_CLK
SD_CLK
SD_CLK
SD_CLK
SD_CLK
Unit
Mhz
ns
ns
ns
ns
ns
ns
ns
ns
Notes
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