MCF5329DS ANALOGICTECH [Advanced Analogic Technologies], MCF5329DS Datasheet - Page 40

• Manufacturer Part Number: MCF5329DS
• Description: MCF5329 ColdFire Microprocessor Data Sheet
• Manufacturer: ANALOGICTECH [Advanced Analogic Technologies]

Preliminary Electrical Characteristics
5.16.2 MII Transmit Signal Timing (FEC_TXD[3:0], FEC_TXEN,
Table 24
The transmitter functions correctly up to a FEC_TXCLK maximum frequency of 25 MHz +1%. There is
no minimum frequency requirement. In addition, the processor clock frequency must exceed twice the
FEC_TXCLK frequency.
The transmit outputs (FEC_TXD[3:0], FEC_TXEN, FEC_TXER) can be programmed to transition from
either the rising or falling edge of FEC_TXCLK, and the timing is the same in either case. This options
allows the use of non-compliant MII PHYs.
Refer to the Ethernet chapter for details of this option and how to enable it.
Figure 27
5.16.3 MII Async Inputs Signal Timing (FEC_CRS and FEC_COL)
Table 25
Figure 28
40
Num
M5
M6
M7
M8
Num
M9
FEC_TXD[3:0] (outputs)
lists MII transmit channel timings.
lists MII asynchronous inputs signal timing.
shows MII transmit signal timings listed in
shows MII asynchronous input timings listed in
FEC_TXER, FEC_TXCLK)
FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER invalid
FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER valid
FEC_TXCLK pulse width high
FEC_TXCLK pulse width low
FEC_TXCLK (input)
FEC_CRS, FEC_COL minimum pulse width
FEC_TXEN
FEC_TXER
MCF5329 ColdFire
Figure 27. MII Transmit Signal Timing Diagram
Characteristic
Characteristic
Table 25. MII Async Inputs Signal Timing
Table 24. MII Transmit Signal Timing
®
Microprocessor Data Sheet, Rev. 0.1
M5
Preliminary
M6
M7
Table
Table
24.
25.
Min
1.5
35%
35%
M8
Min
—
5
Max
—
Max
65%
65%
25
—
Freescale Semiconductor
FEC_TXCLK period
FEC_TXCLK period
FEC_TXCLK period
Unit
Unit
ns
ns