MCF5481 FREESCALE [Freescale Semiconductor, Inc], MCF5481 Datasheet - Page 16

• Manufacturer Part Number: MCF5481
• Description: Microprocessor Electrical Characteristics
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

SDRAM Bus
16
8
9
10
11
The first data beat will be valid before the first rising edge of SDDQS and after the SDDQS write preamble. The remaining
data beats will be valid for each subsequent SDDQS edge.
This specification relates to the required hold time of today’s DDR memories. SDDATA[31:24] is relative to SDDQS3,
SDDATA[23:16] is relative to SDDQS2, SDDATA[15:8] is relative to SDDQS1, and SDDATA[7:0] is relative SDDQS0.
Data input skew is derived from each SDDQS clock edge. It begins with a SDDQS transition and ends when the last data
line becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing
or other factors).
Data input hold is derived from each SDDQS clock edge. It begins with a SDDQS transition and ends when the first data
line becomes invalid.
SDCSn,SDWE,
RAS, CAS
SDBA[1:0]
SDADDR,
SDCLK0
SDCLK1
SDCLK0
SDCLK1
SDDATA
SDDQS
SDDM
MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1
DD4
ROW
CMD
DD1
Figure 12. DDR Write Timing
DD5
COL
DD6
WD1 WD2 WD3 WD4
DD2
DD3
DD7
DD7
DD8
DD8
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