M30280F6HP RENESAS [Renesas Technology Corp], M30280F6HP Datasheet - Page 221

• Manufacturer Part Number: M30280F6HP
• Description: 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES
• Manufacturer: RENESAS [Renesas Technology Corp]

M
R
R
1
e
E
. v
6
NOTES:
J
Table 14.15 Special Mode 2 Specifications
0
C
14.1.4 Special Mode 2 (UART2)
Interrupt request
generation timing
Transfer data format
Transfer clock
Transmit/receive control
Transmission start condition
Reception start condition
Error detection
Select function
2
9
2 /
1. When an external clock is selected, the conditions must be met while if the CKPOL bit in the U2C0 register is
Multiple slaves can be serially communicated from one master. Transfer clock polarity and phase are
selectable. Table 14.15 lists the specifications of Special Mode 2. Table 14.16 lists the registers used in
Special Mode 2 and the register values set. Figure 14.26 shows communication control example for
Special Mode 2.
0 .
2. If an overrun error occurs, bits 8 to 0 in the U2RB register are undefined. The IR bit in the S2RIC register
B
0
8
0
set to “0” (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer
clock), the external clock is in the high state; if the CKPOL bit in the U2C0 register is set to “1” (transmit data
output at the rising edge and the receive data taken in at the falling edge of the transfer clock), the external
clock is in the low state.
remains unchanged.
0
G
4
J
7
a
o r
0 -
. n
u
Item
2
p
3
0
, 1
0
(
M
2
1
0
0
6
7
C
2 /
, 8
page 201
M
1
6
• Transfer data length: 8 bits
• Master mode
Controlled by input/output ports
• Before transmission can start, the following requirements must be met
_
_
• Before reception can start, the following requirements must be met
_
_
_
• For transmission, one of the following conditions can be selected
_
_
• For reception
• Overrun error
• Clock phase setting
C
When transferring data from the UART2 receive register to the U2RB register (at
completion of reception)
the CKDIR bit in the U2MR register is set to “0” (internal clock) : fj/ (2(n+1))
fj = f
• Slave mode
CKDIR bit is set to “1” (external clock selected) : Input from CLK2 pin
ferring data from the U2TB register to the UART2 transmit register (at start of transmission)
data from the UART2 transmit register
This error occurs if the serial I/O started receiving the next data before reading the
U2RB register and received the 7th bit in the the next data
Selectable from four combinations of transfer clock polarities and phases
The TE bit in the U2C1 register is set to "1" (transmission enabled)
The TI bit in the U2C1 register is set to "0" (data present in U2TB register)
The RE bit in the U2C1 register is set to "1" (reception enabled)
The TE bit in the U2C1 register is set to "1" (transmission enabled)
The TI bit in the U2C1 register is set to "0" (data present in the U2TB register)
The U2IRS bit in the U2C1 register is set to "0" (transmit buffer empty): when trans
The U2IRS bit is set to "1" (transfer completed): when the serial I/O finished sending
2 /
f o
8
3
) B
1SIO
8
5
, f
2SIO
(2)
, f
8SIO
, f
32SIO
. n: Setting value in the U2BRG register
Specification
(1)
00
(1)
14. Serial I/O
16
to FF
16