X4323 INTERSIL [Intersil Corporation], X4323 Datasheet - Page 16

• Manufacturer Part Number: X4323
• Description: CPU Supervisor with 32K EEPROM
• Manufacturer: INTERSIL [Intersil Corporation]

TIMING DIAGRAMS
Bus Timing
WP Pin Timing
Write Cycle Timing
Nonvolatile Write Cycle Timing
Notes: (1) t
SDA OUT
Symbol
t
SDA IN
WC
SCL
the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
(1)
SDA
WC
SCL
SDA IN
is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is
SCL
t
WP
SU:STA
8th bit of Last Byte
16
t
HD:STA
t
F
Write Cycle Time
START
Parameter
t
SU:DAT
t
SU:WP
t
HIGH
ACK
X4323, X4325
Clk 1
t
LOW
t
Slave Address Byte
HD:DAT
Condition
Min.
Stop
t
R
t
AA
Typ.
t
WC
t
t
5
HD:WP
DH
Clk 9
(1)
Condition
Start
Max.
10
t
BUF
t
SU:STO
Unit
ms
March 29, 2005
FN8122.0