X5083SI INTERSIL [Intersil Corporation], X5083SI Datasheet - Page 14
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X5083SI
Manufacturer Part Number
X5083SI
Description
CPU Supervisor with 9Kbit SPI EEPROM
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet
1.X5083SI.pdf
(20 pages)
Equivalent A.C. Load Circuit at 5V V
AC Electrical Specifications
NOTES:
DATA INPUT TIMING
DATA OUTPUT TIMING
3. This parameter is periodically sampled and not 100% tested.
4. t
t
t
t
t
t
WC
RO
FO
OUTPUT
SYMBOL
RI
FI
WC
t
(Note 3)
(Note 3)
(Note 3)
f
t
t
f
(Note 3)
LEAD
(Note 4)
t
t
CYC
t
t
SCK
LAG
t
t
SCK
WH
DIS
WL
SU
t
CS
t
HO
H
V
is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle.
SO
1.64kΩ
Clock frequency
Cycle time
CS lead time
CS lag time
Clock HIGH time
Clock LOW time
Data setup time
Data hold time
Input rise time
Input fall time
CS deselect time
Write cycle time
Clock frequency
Output disable time
Output valid from clock low
Output hold time
Output rise time
Output fall time
5V
1.64kΩ
100pF
14
(Over recommended operating conditions, unless otherwise specified)
RESET
PARAMETER
5V
CC
3.3kΩ
30pF
X5083
A.C. Test Conditions
Input pulse levels
Input rise and fall times
Input and output timing level
MIN
300
150
150
130
130
100
20
20
0
0
0
2.7V-5.5V
V
10ns
V
CC
CC
MAX
150
130
3.3
3.3
10
50
50
x 0.1 to V
x 0.5
2
2
September 16, 2005
CC
x 0.9
UNIT
MHz
MHz
ms
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
FN8127.2