X5083SI INTERSIL [Intersil Corporation], X5083SI Datasheet - Page 4

• Manufacturer Part Number: X5083SI
• Description: CPU Supervisor with 9Kbit SPI EEPROM
• Manufacturer: INTERSIL [Intersil Corporation]

Pin Description
Principles of Operation
Power-on Reset
Application of power to the X5083 activates a power-on
reset circuit. This circuit goes LOW at 1V and pulls the
RESET pin active. This signal prevents the system
microprocessor from starting to operate with insufficient
voltage or prior to stabilization of the oscillator. RESET
active also blocks communication to the device through the
SPI interface. When V
200ms (nominal) the circuit releases RESET, allowing the
processor to begin executing code. While V
communications to the device are inhibited.
Low Voltage Monitoring
During operation, the X5083 monitors the V
asserts RESET if supply voltage falls below a preset
minimum V
microprocessor from operating in a power fail or brownout
condition and terminates any SPI communication in
progress. The RESET signal remains active until the voltage
drops below 1V. It also remains active until V
exceeds V
When V
progress are terminated and communications are inhibited
until V
(SOIC/
PDIP)
PIN
1
2
5
6
3
4
8
7
CC
CC
exceeds V
TRIP
TRIP
falls below V
TSSOP
PIN
3
4
7
8
5
6
2
1
. The RESET signal prevents the
for 200ms.
TRIP
CS/WDI Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance state. Unless
RESET
CC
NAME
SCK
V
V
WP
SO
TRIP
SI
CC
SS
for t
exceeds the device V
, any communications in
PURST
4
a nonvolatile write cycle is underway, the device will be in the standby power mode. CS LOW enables the
device, placing it in the active power mode. Prior to the start of any operation after power-up, a HIGH to LOW
transition on CS is required.
Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watchdog timer. The absence of a
HIGH to LOW transition within the watchdog time out period results in RESET going active.
Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The falling edge of the
serial clock (SCK) clocks the data out.
Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this pin. The rising
edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1), addresses and data MSB first.
Serial Clock. The Serial Clock controls the serial bus timing for data input and output. The rising edge of SCK latches
in the opcode, address, or data bits present on the SI pin. The falling edge of SCK changes the data output on the SO
pin.
Write Protect. When WP is LOW, nonvolatile write operations to the memory are prohibited. This “Locks” the
memory to protect it against inadvertent changes when WP is HIGH, the device operates normally.
Ground
Supply Voltage
Reset Output. RESET is an active LOW, open drain output which goes active whenever V
minimum V
RESET goes active if the watchdog timer is enabled and CS remains either HIGH or LOW longer than the
selectable watchdog time out period. A falling edge of CS will reset the watchdog timer. RESET goes active on
power-up at about 1V and remains active for 250ms after the power supply stabilizes.
.
CC
CC
CC
sense level. It will remain active until V
CC
TRIP
< V
level and
returns and
TRIP
value for
X5083
Watchdog Timer
The watchdog timer circuit monitors the microprocessor activity
by monitoring the WDI input. The microprocessor must toggle
the CS/WDI pin periodically to prevent a RESET signal. The
CS/WDI pin must be toggled from HIGH to LOW prior to the
expiration of the watchdog time out period. The state of two
nonvolatile control bits in the status register determine the
watchdog timer period. The microprocessor can change these
watchdog bits with no action taken by the microprocessor
these bits remain unchanged, even after total power failure.
V
The X5083 is shipped with a standard V
voltage. This value will not change over normal operating
and storage conditions. However, in applications where the
standard V
needed in the V
adjusted. The procedure is described below, and uses the
application of a high voltage control signal.
Setting the V
This procedure is used to set the V
value. For example, if the current V
V
the new setting is to be lower than the current setting, then it
is necessary to reset the trip point before setting the new
value.
TRIP
CC
FUNCTION
Threshold Reset Procedure
is 4.6V, this procedure will directly make the change. If
CC
TRIP
rises above the minimum V
TRIP
is not exactly right, or if higher precision is
TRIP
Voltage
value, the X5083 threshold may be
TRIP
TRIP
CC
sense level for 250ms.
CC
to a higher voltage
is 4.4V and the new
CC
threshold (V
falls below the
September 16, 2005
FN8127.2
TRIP
)