X40431 XICOR [Xicor Inc.], X40431 Datasheet - Page 13

• Manufacturer Part Number: X40431
• Description: 4kbit EEPROM, Triple Voltage Monitor with Integrated CPU Supervisor
• Manufacturer: XICOR [Xicor Inc.]

X40430/X40431 – Preliminary Information
A similar operation called “Set Current Address” where
the device will perform this operation if a stop is issued
instead of the second start shown in Figure 14. The
device will go into standby mode after the stop and all
bus activity will be ignored until a start is detected. This
operation loads the new address into the address
counter. The next Current Address Read operation will
read from the newly loaded address. This operation
could be useful if the master knows the next address it
needs to read, but is not ready for the data.
Sequential Read
Sequential reads can be initiated as either a current
address read or random address read. The first Data
Byte is transmitted as with the other modes; however,
the master now responds with an acknowledge, indicat-
ing it requires additional data. The device continues to
output data for each acknowledge received. The master
terminates the read operation by not responding with an
acknowledge and then issuing a stop condition.
Figure 14. Current Address Read Sequence
.
Figure 15. Random Address Read Sequence
– one bit of the slave command byte is a R/W bit. The
REV 1.2.3 11/28/00
R/W bit of the Slave Address Byte defines the opera-
tion to be performed. When the R/W bit is a one, then
a read operation is selected. A zero selects a write
operation.
Signals from
Signals from
the Master
the Slave
SDA Bus
S
a
t
r
t
Signals from
Signals from
the Master
the Slave
SDA Bus
Address
Slave
0
S
a
C
t
r
t
A
K
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Address
Address
Byte
Slave
The data output is sequential, with the data from
address n followed by the data from address n + 1. The
address counter for read operations increments through
all page and column addresses, allowing the entire
memory contents to be serially read during one opera-
tion. At the end of the address space the counter “rolls
over” to address 0000h and the device continues to out-
put data for each acknowledge received. See Figure 16
for the acknowledge and data transfer sequence.
SERIAL DEVICE ADDRESSING
Slave Address Byte
Following a start condition, the master must output a
Slave Address Byte. This byte consists of several parts:
– a device type identifier that is always ‘1010’.
– two bits that provide the device select bits.
– one bit that becomes the MSB of the address.
– After loading the entire Slave Address Byte from the
1
A
C
K
SDA bus, the device compares the device select bits
with the status of the Device Select pins. Upon a cor-
rect compare, the device outputs an acknowledge on
the SDA line.
A
C
K
S
a
r
t
t
Address
Slave
Data
Characteristics subject to change without notice.
1
A
C
K
S
o
p
t
Data
S
o
p
t
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