X40431 XICOR [Xicor Inc.], X40431 Datasheet - Page 6

• Manufacturer Part Number: X40431
• Description: 4kbit EEPROM, Triple Voltage Monitor with Integrated CPU Supervisor
• Manufacturer: XICOR [Xicor Inc.]

X40430/X40431 – Preliminary Information
Note: This operation does not corrupt the memory
array.
Setting a Lower V
In order to set V
present value, then V
ing to the procedure described below. Once V
has been “reset”, then V
voltage using the procedure described in “Setting a
Higher V
Resetting the V
To reset a V
age (Vp) to the WDO pin before a START condition is
set up on SDA. Next, issue on the SDA pin the Slave
Address A0h followed by the Byte Address 03h for
V
by 00h for the Data Byte in order to reset V
STOP bit following a valid write operation initiates the
programming sequence. Pin WDO must then be
brought LOW to complete the operation.
After being reset, the value of V
nal value of 1.7V or lesser.
Note: This operation does not corrupt the memory
array.
Control Register
The Control Register provides the user a mechanism
for changing the Block Lock and Watchdog Timer set-
tings. The Block Lock and Watchdog Timer bits are
nonvolatile and do not change when power is removed.
Figure 5. Sample V
REV 1.2.3 11/28/00
TRIP1
V
Adj.
TRIP1
, 0Bh for V
TRIPx
TRIPx
Voltage”.
TRIPx
voltage, apply the programming volt-
TRIP2
TRIPx
TRIPx
TRIP
V
TRIPx
Adj.
TRIP2
Voltage
, and 0Fh for V
TRIPx
V2FAIL
Voltage (x=1, 2, 3)
to a lower voltage than the
Reset Circuit
must first be “reset” accord-
can be set to the desired
TRIPx
RESET
becomes a nomi-
TRIP3
TRIPx
, followed
www.xicor.com
TRIPx
. The
1
6
2
7
X40430
The Control Register is accessed with a special pre-
amble in the slave byte (1011) and is located at
address 1FFh. It can only be modified by performing a
byte write operation directly to the address of the regis-
ter and only one data byte is allowed for each register
write operation. Prior to writing to the Control Register,
the WEL and RWEL bits must be set using a two step
process, with the whole sequence requiring 3 steps.
See "Writing to the Control Registers" on page 7.
The user must issue a stop, after sending this byte to
the register, to initiate the nonvolatile cycle that stores
WD1, WD0, PUP1, PUP0, BP1, and BP0. The X40430
will not acknowledge any data bytes written after the
first byte is entered.
The state of the Control Register can be read at any
time by performing a random read at address 1FFh,
using the special preamble. Only one byte is read by
each register read operation. The master should
supply a stop condition to be consistent with the bus
protocol.
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit must be set to “1” prior to a write to the
Control Register.
PUP1 WD1 WD0
7
13
14
9
8
6
5
Characteristics subject to change without notice.
Adjust
Run
BP1
4
V
P
BP0
3
RWEL WEL PUP0
SCL
SDA
2
µC
1
6 of 24
0