X4645 INTERSIL [Intersil Corporation], X4645 Datasheet

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X4645

Manufacturer Part Number
X4645
Description
CPU Supervidor with 64K EEPROM
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet
CPU Supervisor with 64K EEPROM
FEATURES
• Selectable watchdog timer
• Low V
• Low power CMOS
• 64Kbits of EEPROM
• Built-in inadvertent write protection
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available packages
BLOCK DIAGRAM
—Four standard reset threshold voltages
—Adjust low V
—Reset signal valid to V
—<20µA max standby current, watchdog on
—<1µA standby current, watchdog off
—3mA active current
—64-byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
—Power-up/power-down protection circuitry
—8-lead SOIC
—8-lead TSSOP
V
SDA
SCL
CC
WP
special programming sequence
S0
S1
CC
detection and reset assertion
CC
reset threshold voltage using
V
Reset Logic
CC
Command
Register
Decode &
®
Control
Logic
Threshold
Data
1
CC
Watchdog Transition
= 1V
Data Sheet
Detector
V
TRIP
EEPROM Array
Protect Logic
1-888-INTERSIL or 1-888-352-6832
Register
Status
+
-
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
DESCRIPTION
The X4643/5 combines four popular functions, Power-
on Reset Control, Watchdog Timer, Supply Voltage
Supervision, and Serial EEPROM Memory in one pack-
age. This combination lowers system cost, reduces
board space requirements, and increases reliability.
Applying power to the device activates the power-on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable time
out interval, the device activates the RESET/RESET
signal. The user selects the interval from three preset
values. Once selected, the interval does not change,
even after cycling the power.
The device’s low V
user’s system from low voltage conditions, resetting
the system when V
V
returns to proper operating level and stabilizes. Four
industry standard V
however, Intersil’s unique circuits allow the threshold
to be reprogrammed to meet custom requirements or
to fine-tune the threshold for applications requiring
higher precision.
CC
trip point. RESET/RESET is asserted until V
Power-on and
Timer Reset
Low Voltage
March 29, 2005
Watchdog
Generation
Watchdog
Timebase
All other trademarks mentioned are the property of their respective owners.
Reset &
Reset
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
CC
CC
TRIP
detection circuitry protects the
falls below the set minimum
thresholds are available,
X4643, X4645
64K, 8K x 8 Bit
RESET (X4643/5)
RESET (X4645)
FN8123.0
CC

Related parts for X4645

X4645 Summary of contents

Page 1

... All other trademarks mentioned are the property of their respective owners. X4643, X4645 64K Bit FN8123.0 detection circuitry protects the CC falls below the set minimum CC CC thresholds are available, TRIP RESET (X4643/5) RESET (X4645) Copyright Intersil Americas Inc. 2005. All Rights Reserved ...

Page 2

... SDA 6 8 SCL X4643, X4645 SCL SDA SCL SDA V SS RESET/RESET Device Select Input Device Select Input Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which goes active whenever V will remain active until V ...

Page 3

... SCL SDA A0h 3 X4643, X4645 WATCHDOG TIMER The Watchdog Timer circuit monitors the microprocessor activity by monitoring the SDA and SCL pins. The microprocessor must toggle the SDA pin HIGH to LOW periodically, while SCL is HIGH (this is a start bit) prior to the expiration of the watchdog time out period to prevent a RESET/RESET signal ...

Page 4

... A0h Figure 3. Sample V Reset Circuit TRIP 4.7K RESET V TRIP Adj. 4 X4643, X4645 Resetting the higher or This procedure is used to set the V TRIP voltage level. For example, if the current V and the new V be reset. When V thing less than 1.7V. This procedure must be used to TRIP set the voltage to a lower value ...

Page 5

... The Control Register is accessed at address FFFFh. It can only be modified by performing a byte write opera- tion directly to the address of the register and only one data byte is allowed for each register write operation. 5 X4643, X4645 V Programming TRIP Execute Reset V ...

Page 6

... Writes OK HIGH 1 Writes OK 6 X4643, X4645 acknowledge will be issued after the Data Byte). The WEL bit is set by writing a “1” to the WEL bit and zeroes to the other bits of the control register. Once set, WEL remains set until either it is reset to 0 (by writing a “ ...

Page 7

... Figure 5. Valid Data Changes on the SDA Bus SCL SDA 7 X4643, X4645 – The RWEL bit cannot be reset without writing to the nonvolatile control bits in the control register, power cycling the device or attempting a write to a write protected block. To illustrate, a sequence of writes to the device con- sisting of [02H, 06H, 02H] will reset all of the nonvola- tile bits in the Control Register to 0 ...

Page 8

... Data Output from Receiver Start 8 X4643, X4645 Serial Stop Condition All communications must be terminated by a stop con- dition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the device into the Standby power mode after a read sequence ...

Page 9

... Signals from the Slave 9 X4643, X4645 eight bits of data. After receiving the 8 bits of the Data Byte, the device again responds with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the device begins the inter- nal write cycle to the nonvolatile memory. During this internal write cycle, the device inputs are disabled, so the device will not respond to any requests from the master ...

Page 10

... ACK will be returned. If the device has completed the write operation, an ACK will be returned and the host can then proceed with the read or write operation. Refer to the flow chart in Figure 11. 10 X4643, X4645 Address Pointer Address Ends Here 60 Addr = 8 Figure 11 ...

Page 11

... Signals from the Slave 11 X4643, X4645 Upon receipt of the Slave Address Byte with the R/W bit set to one, the device issues an acknowledge and then transmits the eight bits of the Data Byte. The master terminates the read operation when it does not respond with an acknowledge during the ninth clock and then issues a stop condition ...

Page 12

... When the R/W bit is a one, then a read operation is selected. A zero selects a write operation. Refer to Figure 15. 12 X4643, X4645 the master now responds with an acknowledge, indicat- ing it requires additional data. The device continues to output data for each acknowledge received. The master terminates the read operation by not responding with an acknowledge and then issuing a stop condition ...

Page 13

... A three step sequence is required before writing into the Control Register to change Watchdog Timer or block lock settings. – The WP pin, when held HIGH, and WPEN bit at logic HIGH will prevent all writes to the Control Register. 13 X4643, X4645 Device Select ...

Page 14

... Min. and V Max. are for reference only and are not tested X4643, X4645 COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied ...

Page 15

... Cb Capacitive load for each bus line Notes: (1) Typical values are for T = 25°C and total capacitance of one bus line in pF. 15 X4643, X4645 = 5V) CC Parameter A.C. TEST CONDITIONS Input pulse levels Input rise and fall times Input and output timing levels = 0 ...

Page 16

... the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. 16 X4643, X4645 t t HIGH LOW ...

Page 17

... Reset Valid V RVALID CC Notes: (8) This parameter is periodically sampled and not 100% tested. SDA vs. RESET Timing t RSP SCL SDA RESET Note: All inputs are ignored during the active reset period (t 17 X4643, X4645 t PURST t PURST t RPD Parameter t RSP t >t <t RSP WDO WDO ...

Page 18

... Program Voltage repeatability (Successive program operations. Programmed at tr TRIP 25°C Program variation after programming (0-75°C). (Programmed at 25°C.) tv TRIP V programming parameters are periodically sampled and are not 100% tested. TRIP 18 X4643, X4645 V TRIP 01h or 03h 00h Description applied-V CC TRIP Program Voltage accuracy [(V applied-V CC Min. ...

Page 19

... PACKAGING INFORMATION 8-Lead Plastic Small Outline Gull Wing Package Type S Pin 1 Index 0.010 (0.25) 0.020 (0.50) 0° - 8° 0.016 (0.410) 0.037 (0.937) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 19 X4643, X4645 Pin 1 0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00) (4X) 7° 0.050 (1.27) X 45° 0.0075 (0.19) 0.250" 0.010 (0.25) FOOTPRINT 0 ...

Page 20

... PACKAGING INFORMATION 0° - 8° See Detail “A” NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 20 X4643, X4645 8-Lead Plastic, TSSOP, Package Type V .025 (.65) BSC .169 (4.3) .177 (4.5) .114 (2.9) .122 (3.1) .047 (1.20) .0075 (.19) .002 (.05) .006 (.15) .0118 (.30) .010 (.25) Gage Plane Seating Plane .019 (.50) .029 (.75) Detail A (20X) ...

Page 21

... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 21 X4643, X4645 Operating Part Number RESET Temperature Range (Active LOW) 0° ...

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