X40231 INTERSIL [Intersil Corporation], X40231 Datasheet
X40231
Related parts for X40231
X40231 Summary of contents
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... ©2000 Intersil Inc., Patents Pending (VTRIP are user programmable) 1,2,3 1 X40231, X40233, X40235, X40237, X40239 Integrated System Management IC April 11, 2005 DESCRIPTION The X4023x family of Integrated System Manage- ment ICs combine CPU Supervisor functions (V Power-onpower-on Reset (POR) circuitry, two addi- tional programmable voltage monitor inputs with soft- ...
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... X40231, X40233, X40235, X40237, X40239 PIN CONFIGURATION SINGLE XDCP X40231 16 Pin SOIC RESET V3MON 14 V2FAIL V3FAIL 4 13 V2MON SCL SDA 8 VSS 9 DUAL XDCP X40237 16 Pin SOIC RESET ...
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... X40231, X40233, X40235, X40237, X40239 X40231 PIN ASSIGNMENT SOIC Name Connect Connect V3MON Voltage Monitor Input. V3MON i s the input to a non-inverting voltage comparator circuit. When the V3MON input is higher than 3 V3MON the V threshold voltage, V3FAIL makes a transition to a HIGH level. Connect V3MON to V TRIP3 not used ...
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... X40231, X40233, X40235, X40237, X40239 X40233 PIN ASSIGNMENT SOIC Name Connect Connect V3MON Voltage Monitor Input. V3MON is the input to a non-inverting voltage comparator circuit. When the V3MON input is higher than 3 V3MON the V threshold voltage, V3FAIL makes a transition to a HIGH level. Connect V3MON to V TRIP3 not used ...
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... X40231, X40233, X40235, X40237, X40239 X40235 PIN ASSIGNMENT SOIC Name R 1 Connection to end of resistor array for (the 256 Tap) DCP Connection to terminal equivalent to the “Wiper” mechanical potentiometer for DCP. W2 V3MON Voltage Monitor Input. V3MON is the input to a non-inverting voltage comparator circuit. When the V3MON input is higher than ...
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... X40231, X40233, X40235, X40237, X40239 X40237 PIN ASSIGNMENT SOIC Name R 1 Connection to end of resistor array for (the 256 Tap) DCP2 Connection to terminal equivalent to the “Wiper” mechanical potentiometer for DCP2. W2 V3MON Voltage Monitor Input. V3MON is the input to a non-inverting voltage comparator circuit. When the V3MON input is higher than ...
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... X40231, X40233, X40235, X40237, X40239 X40239 PIN ASSIGNMENT SOIC Name R 1 Connection to end of resistor array for (the 256 Tap) DCP2 Connection to terminal equivalent to the “Wiper” mechanical potentiometer for DCP2. W2 V3MON Voltage Monitor Input. V3MON is the input to a non-inverting voltage comparator circuit. When the V3MON input is higher than ...
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... X40231, X40233, X40235, X40237, X40239 SCL SDA Figure 1. DETAILED DEVICE DESCRIPTION The X4023x combines One or Two Intersil Digitally Controlled Potentiometer (XDCP) power-on reset control, V low voltage reset control, CC two supplementary voltage monitors with independent outputs, and integrated EEPROM with Block Lock™ ...
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... X40231, X40233, X40235, X40237, X40239 SCL SDA Figure 2. Serial Start Condition All commands are preceded by the START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The device continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition has been met ...
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... X40231, X40233, X40235, X40237, X40239 Depending upon the operation to be performed on each of these individual parts Byte protocol is used. All operations however must begin with the Slave Address Byte being issued on the SDA pin. The Slave address selects the part of the X4023x to be addressed, and specifies if a Read or Write operation performed ...
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... X40231, X40233, X40235, X40237, X40239 Byte load completed by issuing STOP. Enter ACK Polling Issue START Issue Slave Address Byte (Read or Write) NO ACK returned? YES NO High Voltage Cycle complete. Continue command sequence? YES Continue normal Read or Write command sequence PROCEED Figure 5. Acknowledge Polling Sequence ...
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... X40231, X40233, X40235, X40237, X40239 TRANS 0 A nonvolatile write to a DCP will change the “wiper posi- tion” by simultaneously writing new data to the associ- ated WCR and NVM. Therefore, the new “wiper position” setting is recalled into the WCR after V is powered down and then powered back up ...
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... X40231, X40233, X40235, X40237, X40239 SLAVE ADDRESS BYTE T Figure 9. DCP Write Operation A write to DCPx (x=0,1,2) can be performed using the three byte command sequence shown in Figure 9. In order to perform a write operation on a particular DCP, the Write Enable Latch (WEL) bit of the CR Reg- ister must first be set (See “ ...
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... X40231, X40233, X40235, X40237, X40239 S Signals from t Slave the Master a Address r t SDA Bus Signals from the Slave DCP Read Operation A read of DCPx (x = 0,1,2) can be performed using the three byte random read command sequence shown in Figure 10. The master issues the START condition and the Slave Address Byte 10101110 which specifies that a “ ...
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... X40231, X40233, X40235, X40237, X40239 S Signals from t a the Master r t SDA Bus Signals from the Slave Figure 12. EEPROM Page Write Operation EEPROM Byte Write In order to perform an EEPROM Byte Write operation to the EEPROM array, the Write Enable Latch (WEL) bit of the CR Register must first be set (See “BL1, BL0: Block Lock protection bits - (Nonvolatile)” ...
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... X40231, X40233, X40235, X40237, X40239 7 bytes Figure 13. Example: Writing 12 bytes to a 16-byte page starting at location 11. Signals from the Master Figure 14. Current EEPROM Address Read Sequence Current EEPROM Address Read Internally the device contains an address counter that maintains the address of the last word read incre- mented by one ...
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... X40231, X40233, X40235, X40237, X40239 Signals from S the Master SDA Bus Signals from the Slave Figure 15. Random EEPROM Address Read Sequence The master terminates the read operation by not responding with an ACKNOWLEDGE and instead issuing a STOP condition (Refer to Figure 15). ...
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... X40231, X40233, X40235, X40237, X40239 CS3 CS7 CS6 CS4 CS5 PUP1 BL1 V2FS V3FS BL0 Bit(s) Description WEL Write Enable Latch bit RWEL Register Write Enable Latch bit V2FS V2MON Output Flag Status V3FS V3MON Output Flag Status BL1 - BL0 ...
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... X40231, X40233, X40235, X40237, X40239 When the Block Lock bits of the CR register are set to something other than BL1 = 0 and BL0 = 0, then the “wiper position” of the DCPs cannot be changed - i.e. DCP write operations cannot be conducted: BL1 BL0 DCP Write Operation Permissible 0 0 YES (Default) ...
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... X40231, X40233, X40235, X40237, X40239 Prior to writing to the CR register, the WEL and RWEL bits must be set using a two step process, with the whole sequence requiring 3 steps —Write a 02H to the CR Register to set the Write Enable Latch (WEL). This is a volatile operation, so there is no delay after the write ...
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... X40231, X40233, X40235, X40237, X40239 MR: Manual Reset The RESET output can be forced HIGH externally using the Manual Reset (MR) input de-bounced, TTL compatible input, and so it may be operated by con- necting a push-button directly from V RESET remains HIGH for time t returned to its LOW state (See Figure 19). An exter- nal “ ...
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... X40231, X40233, X40235, X40237, X40239 V2MON Monitoring The X4023x asserts the V2FAIL output HIGH if the voltage V2MON exceeds the corresponding V threshold (See Figure 21). The bit V2FS in the CR reg- ister is then set to a “0” (assuming that it has been set to “1” after system initialization). ...
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... X40231, X40233, X40235, X40237, X40239 Setting a Higher V Voltage (x = 1,2,3) TRIPx To set a V threshold to a new voltage which is TRIPx higher than the present threshold, the user must apply the desired V threshold voltage to the correspond- TRIPx ing input pin (V , V2MON or V3MON). Then, a pro- CC gramming voltage (Vp) must be applied to the WP pin before a START condition is set up on SDA ...
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... X40231, X40233, X40235, X40237, X40239 For example, the desired threshold for V 3.0 V, and a test voltage of 3.4 V was applied to the input pin V2MON (after applying power to V age is decreased, and found to trip the associated output level of pin V2FAIL from a LOW to a HIGH, when V2MON reaches 3 ...
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... X40231, X40233, X40235, X40237, X40239 ABSOLUTE MAXIMUM RATINGS Temperature under Bias Storage Temperature Voltage on WP pin (With respect to VSS) Voltage on other pins (With respect to VSS) Voltage Voltage 0,1,2. Referenced to V D.C. Output Current (SDA,RESETRESET,V2FAIL,V3FAIL) Lead Temperature (Soldering, 10 seconds) Supply Voltage Limits (Applied V ...
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... X40231, X40233, X40235, X40237, X40239 TIMING DIAGRAMS Figure 27. Bus Timing t F SCL t SU:STA t HD:STA SDA IN SDA OUT Figure 28. WP Pin Timing START SCL SDA IN WP Figure 29. Write Cycle Timing SCL 8th bit of last byte SDA HIGH LOW t SU:DAT t HD:DAT Clk 1 ...
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... X40231, X40233, X40235, X40237, X40239 Figure 30. Power-Up and Power-Down Timing Volts RESET 0 Volts MR 0 Volts Figure 31. Manual Reset Timing Diagram MR RESET V CC Figure 32. V2MON, V3MON Timing Diagram RPDx VxFAIL V CC Note : PURST t PURST t RPD t MRPW 0 Volts ...
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... X40231, X40233, X40235, X40237, X40239 Figure 33. V Programming Timing Diagram (x=1,2,3). TRIPX V , V2MON, V3MON CC t TSU VPS SCL SDA NOTE : V1/V Figure 34. DCP “Wiper Position” Timing Rwx (x=0,1,2) R WX( tap position SCL SDA SLAVE ADDRESS BYTE ...
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... X40231, X40233, X40235, X40237, X40239 D.C. OPERATING CHARACTERISTICS Symbol Parameter V CC Current into V Pin (X4023x: Active) CC (1) I Read memory array CC 1 Write nonvolatile memory V Current into V Pin (X4023x:Standby) CC With 2-Wire bus activity ( 2-Wire bus activity V = 3.5V CC Input Leakage Current I LI ...
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... X40231, X40233, X40235, X40237, X40239 A.C. CHARACTERISTICS (See Figure 27, Figure 28, Figure 29) Symbol f SCL Clock Frequency SCL (5) t Pulse width Suppression Time at inputs IN t SCL LOW to SDA Data Out Valid AA t Time the bus free before start of new transmission BUF t Clock LOW Time ...
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... X40231, X40233, X40235, X40237, X40239 POTENTIOMETER CHARACTERISTICS Symbol Parameter R End to End Resistance Tolerance TOL V R Terminal Voltage (x = 0,1,2) RHx Terminal Voltage (x = 0,1,2) RLx L (1) P Power Rating R R DCP Wiper Resistance W I Wiper Current W Noise (2) Absolute Linearity (3) Relative Linearity R Temperature Coefficient TOTAL Ratiometric Temperature ...
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... X40231, X40233, X40235, X40237, X40239 1,2,3) PROGRAMMING PARAMETERS (See Figure 33) TRIPX Parameter t V Program Enable Voltage Setup time VPS TRIPx t V Program Enable Voltage Hold time VPH TRIPx t V Setup time TSU TRIPx t V Hold (stable) time THD TRIPx V Program Enable Voltage Off time ...
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... X40231, X40233, X40235, X40237, X40239 APPENDIX 1 DCP1 (100 Tap) Tap position to Data Byte translation Table Tap Position Decimal 120 76 119 . . . . Data Byte Binary 0000 0000 0000 0001 ...
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... X40231, X40233, X40235, X40237, X40239 APPENDIX 2 DCP1 (100 Tap) tap position to Data Byte translation algorithm example. unsigned DCP1_TAP_Position(int tap_pos) { int block; int i; int offset; int wcr_val; offset = 0; block = tap_pos / 25; if (block < 0) return ((unsigned)0); else if (block < switch(block) { case (0): return ((unsigned)tap_pos) ; ...
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... X40231, X40233, X40235, X40237, X40239 16-Lead Plastic, SOIC (300-mil body), Package Code S16 PIN 1 INDEX PIN 1 0.014 (0.35) 0.020 (0.51) (4X) 7° 0.050 (1.27) 0.010 (0.25) X 45° 0.020 (0.50) 0° ° 0.015 (0.40) 0.050 (1.27) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 35 0.290 (7.37) 0.299 (7.60) 0.403 (10.2 ) 0.413 ( 10.5) 0.003 (0.10) 0.012 (0.30) 0.0075 (0.19) 0.420" ...
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... X40231, X40233, X40235, X40237, X40239 ORDERING INFORMATION Device x DEVICE 1 X40231 3 X40233 5 X40235 7 X40237 9 X40239 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...