X40231 INTERSIL [Intersil Corporation], X40231 Datasheet - Page 21

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X40231

Manufacturer Part Number
X40231
Description
Triple Voltage Monitors, POR, 2 kbit EEPROM MEMORY, and Single/Dual DCP
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet
MR: Manual Reset
The RESET output can be forced HIGH externally using
the Manual Reset (MR) input. MR is a de-bounced, TTL
compatible input, and so it may be operated by con-
necting a push-button directly from V
RESET remains HIGH for time t
returned to its LOW state (See Figure 19). An exter-
nal “pull down” resistor is required to hold this pin
(normally) LOW.
X4023x Write Permission Status
Block Lock
BL0
x
1
0
x
1
0
Bits
BL1
1
x
0
1
x
0
Signals from the
Master
Signals from the
Slave
SDA Bus
WP
0
1
1
1
0
0
DCP Volatile Write
Permitted
21
YES
YES
NO
NO
NO
NO
S
a
t
r
t
X40231, X40233, X40235, X40237, X40239
1
0 1 0 0 1 0
Figure 20. CR Register Read Command Sequence
PURST
Address
CC
Slave
to the MR pin.
after MR has
“Dummy” Write
DCP Nonvolatile
Write Permitted
0
A
C
K
WRITE Operation
YES
NO
NO
NO
NO
NO
Address Byte
Not in locked region
Not in locked region
A
C
K
Write to EEPROM
S
a
Yes (All Array)
t
r
t
RESET
1 0 1 0 0 1 0
V
MR
Permitted
Figure 19. Manual Reset Response
CC
Address
NO
NO
NO
Slave
0 Volts
0 Volts
0 Volts
1
READ Operation
A
C
K
CS7 … CS0
Volatile Bits
Data
YES
YES
YES
YES
YES
YES
Write to CR Register
Permitted
t
PURST
S
o
p
t
Nonvolatile Bits
V
TRIP1
YES
YES
YES
NO
NO
NO
April 11, 2005
FN8115.0

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