LF3320QC15 LODEV [LOGIC Devices Incorporated], LF3320QC15 Datasheet - Page 4

• Manufacturer Part Number: LF3320QC15
• Description: Horizontal Digital Image Filter
• Manufacturer: LODEV [LOGIC Devices Incorporated]

DEVICES INCORPORATED
ROUT
In Single Filter Mode, ROUT
12-bit registered cascade output port.
ROUT
connected to RIN
In Dual Filter Mode, ROUT
registered output port for the upper four
bits of the 16-bit Filter B output. In this
mode, ROUT
Controls
LDA — Coefficient A Load
When LDA is LOW, data on CFA
latched into the Filter A LF Interface
on the rising edge of CLK. When LDA is
HIGH, data is not loaded into the Filter
A LF Interface
Interface
LOW transition of LDA is required in
order for the input circuitry to function
properly. Therefore, LDA must be set
HIGH immediately after power up to
ensure proper operation of the input
circuitry (see the LF Interface
for a full discussion).
CENA — Coefficient Address Enable A
When CENA is LOW, data on CAA
is latched into Coefficient Address
Register A on the rising edge of CLK.
When CENA is HIGH, data on CAA
is not latched and the register’s
contents will not be changed.
LDB — Coefficient B Load
When LDB is LOW, data on CFB
latched into the Filter B LF Interface
on the rising edge of CLK. When LDB is
HIGH, data is not loaded into the Filter
B LF Interface
Interface
LOW transition of LDB is required in
order for the input circuitry to function
properly. Therefore, LDB must be set
HIGH immediately after power up to
ensure proper operation of the input
circuitry (see the LF Interface
for a full discussion).
11-0
11-0
TM
TM
— Reverse Cascade Output
on one device should be
for data input, a HIGH to
for data input, a HIGH to
11-4
TM
TM
. When enabling the LF
. When enabling the LF
is disabled.
11-0
of another LF3320.
3-0
11-0
TM
TM
is a 4-bit
section
section
is a
11-0
11-0
TM
TM
7-0
is
7-0
is
CENB — Coefficient Address Enable B
When CENB is LOW, data on CAB
is latched into Coefficient Address
Register B on the rising edge of CLK.
When CENB is HIGH, data on CAB
is not latched and the register’s
contents will not be changed.
TXFRA — Filter A LIFO Transfer
TXFRA is used to change which LIFO
in the data reversal circuitry sends
data to the reverse data path and
which LIFO receives data from the
forward data path in Filter A. When
TXFRA goes LOW, the LIFO sending
data to the reverse data path becomes
the LIFO receiving data from the
forward data path, and the LIFO
receiving data from the forward data
path becomes the LIFO sending data to
the reverse data path. The device must
see a HIGH to LOW transition of
TXFRA in order to switch LIFOs.
TXFRA is latched on the rising edge of
CLK.
TXFRB — Filter B LIFO Transfer
TXFRB is used to change which LIFO
in the data reversal circuitry sends
data to the reverse data path and
which LIFO receives data from the
forward data path in Filter B. When
TXFRB goes LOW, the LIFO sending
data to the reverse data path becomes
the LIFO receiving data from the
forward data path, and the LIFO
receiving data from the forward data
path becomes the LIFO sending data to
the reverse data path. The device must
see a HIGH to LOW transition of
TXFRB in order to switch LIFOs.
TXFRB is latched on the rising edge of
CLK.
ACCA — Accumulator A Control
When ACCA is HIGH, Accumulator A
is enabled for accumulation and the
Accumulator A Output Register is
Control
Control
2-4
Horizontal Digital Image Filter
7-0
7-0
disabled for loading. When ACCA is
LOW, no accumulation is performed
and the Accumulator A Output Register
is enabled for loading. ACCA is latched
on the rising edge of CLK.
ACCB — Accumulator B Control
When ACCB is HIGH, Accumulator B
is enabled for accumulation and the
Accumulator B Output Register is
disabled for loading. When ACCB is
LOW, no accumulation is performed
and the Accumulator B Output Regis-
ter is enabled for loading. ACCB is
latched on the rising edge of CLK.
SHENA — Filter A Shift Enable
In Dual Filter Mode, SHENA enables
or disables the loading of data into the
Input (DIN
Registers. When SHENA is LOW, data
is latched into the Input/Cascade
Registers and shifted through the I/D
Registers on the rising edge of CLK.
When SHENA is HIGH, data can not
be loaded into the Input/Cascade
Registers or shifted through the I/D
Registers and their contents will not be
changed.
In Single Filter Mode, SHENA also
enables or disables the loading of data
into the Reverse Cascade Input (RIN
0
Cascade Output (ROUT
I/D Registers. It is important to note
that in Single Filter Mode, both SHENA
and SHENB should be connected
together. Both must be active to enable
data loading in Single Filter Mode.
SHENA is latched on the rising edge of
CLK.
SHENB — Filter B Shift Enable
In Dual Filter Mode, SHENB enables or
disables the loading of data into the
Reverse Cascade Input (RIN
Cascade Output (COUT
Cascade Output (ROUT
I/D Registers. When SHENB is LOW,
data is latched into the Cascade Regis-
ters and shifted through the I/D
), Cascade Output (COUT
Video Imaging Products
11-0
) and Filter A I/D
11-0
3-0
11-0
08/16/2000–LDS.3320-N
) and Filter B
11-0
), Reverse
) and Filter B
LF3320
11-0
), Reverse
),
11-