LF3321 LODEV [LOGIC Devices Incorporated], LF3321 Datasheet - Page 8

• Manufacturer Part Number: LF3321
• Description: Horizontal Digital Image Filter Improved Performance
• Manufacturer: LODEV [LOGIC Devices Incorporated]

DEVICES INCORPORATED
Rounding
Output Select
Output Limiting
Coefficient
Banks
LOGIC Devices Incorporated
The overall filter output (Single Filter Mode) or Filter A and B outputs (Dual Filter Mode) may be rounded by
adding the contents of one of the sixteen Filter A or B round registers to the overall filter, Filter A, or Filter
B outputs (see Figure 10). The Filter A round registers are used for the overall filter (Single Filtermode)
or Filter A (Dual Filter Mode). The Filter B round registers are used for Filter B (Dual Filter Mode). Each
round register is 32-bits wide and user-programmable. This allows the filter’s output to be rounded to any
precision required. Since any 32-bit value may be programmed into the round registers, the device can
support complex rounding algorithms as well as standard Half-LSB rounding. RSLA3-0 determines which
of the sixteen Filter A round registers are used in the Filter A rounding circuitry. RSLB3-0 determines
which of the sixteen Filter B round registers are used in the Filter B rounding circuitry. A value of 0 on
RSLA/RSLB3-0 selects Filter A/B round register 0. A value of 1 selects Filter A/B round register 1 and so
on. RSLA/RSLB3-0 may be changed every clock cycle if desired. This allows the rounding algorithm to be
changed every clock cycle. This is useful when filtering interleaved data. If rounding is not desired, a round
register should be loaded with 0 and selected as the register used for rounding. Round register loading is
discussed in the LF Interface
The word width of the overall filter, Filter A, and Filter B outputs is 32-bits. However, only 16-bits may be
sent to DOUT15-0 (Single or Dual Filter Modes) and COUT11-0/ROUT3-0 (Dual Filter Mode). The Filter
A/B select circuitry determines which 16-bits are passed (see Table 20). The Filter A/B select registers
control the Filter A/B select circuitry. There are sixteen Filter A and B select registers. The Filter A select
registers are used for the overall filter (Single Filter Mode) or Filter A (Dual Filter Mode). The Filter B select
registers are used for Filter B (Dual Filter Mode). Each select register is 5 bits wide and user-programmable.
RSLA3-0 determines which of the sixteen Filter A select registers are used in the Filter A select circuitry.
RSLB3-0 determines which of the sixteen Filter B select registers are used in the Filter B select circuitry.
A value of 0 on RSLA/RSLB3-0 selects Filter A/B select register 0. A value of 1 selects Filter A/B select
register 1 and so on. RSLA/RSLB3-0 may be changed every clock cycle if desired. This allows the 16-bit
window to be changed every clock cycle. This is useful when filtering interleaved data. Select register
loading is discussed in the LF Interface
An output limiting function is provided for the overall filter, Filter A, and Filter B outputs. The Filter A limiting
circuitry is used to limit the overall filter output (Single Filter Mode) and the Filter A output (Dual Filter
Mode). The Filter B limiting circuitry is used to limit the Filter B output (Dual Filter Mode). The Filter
A and B limit registers determine the valid range of output values for the Filter A and B limiting circuitry
respectively. There are sixteen 32-bit user-programmable limit registers for both Filters A and B. The Filter
A limit registers are used for the overall filter (Single Filter Mode) or Filter A (Dual Filter Mode). The Filter
B limit registers are used for Filter B (Dual Filter Mode). RSLA3-0 determines which of the sixteen Filter
A limit registers are used in the Filter A limit circuitry. RSLB3-0 determines which of the sixteen Filter B
limit registers are used in the Filter B limit circuitry. A value of 0 on RSLA/RSLB3-0 selects Filter A/B limit
register 0. A value of 1 selects Filter A/B limit register 1 and so on. Each limit register contains an upper
and lower limit value. If the value fed to the limiting circuitry is less than the lower limit, the lower limit value
is passed as the filter output. If the value fed to the limiting circuitry is greater than the upper limit, the upper
limit value is passed as the filter output. Bit 1 and 0 in Configuration Register 4 enable and disable Filter A
and B limiting respectively. RSLA/RSLB3-0 may be changed every clock cycle if desired. This allows the
limit range to be changed every clock cycle. This is useful when filtering interleaved data. When loading
limit values into the device, the upper limit must be greater than the lower limit. Limit register loading is
discussed in the LF Interface
The coefficient banks store the coefficients which feed into the multipliers in Filters A and B. There is a
separate bank for each multiplier. Each bank can hold 256 12-bit coefficients. The banks are loaded using
an LF Interface
is discussed in the LF Interface
Functional Description
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. There is a separate LF Interface
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for the Filter A and B banks. Coefficient bank loading
Horizontal Digital Image Filter
Improved Performance
Video Imaging Products
Feb 5, 2003 LDS.3321-A
LF3321