78P2352-IEL TERIDIAN [Teridian Semiconductor Corporation], 78P2352-IEL Datasheet - Page 7

• Manufacturer Part Number: 78P2352-IEL
• Description: Dual Channel OC-3/ STM1-E/ E4 LIU
• Manufacturer: TERIDIAN [Teridian Semiconductor Corporation]

Transmit Driver
In CMI (electrical) mode, the CMIxP/N pins are
biased and terminated off-chip. They interface to
75Ω
transformer and coaxial RF connectors. Reference
application
guidelines.
The transmitter encodes the data using CMI line
coding and shapes an analog signal to meet the
appropriate ITU-T G.703 template. The CMI outputs
are tri-stated during transmit disable and transmit
power-down for redundancy applications and power-
savings.
When the CMI pin is low, the chip is in Fiber
(NRZ pass-through) mode and interfaces directly to
an optical transceiver module. The ECLxP/N pins
are internally biased and output NRZ data at
LVPECL levels.
decoder are disabled in Fiber (NRZ) mode.
Clock Synthesizer
The transmit clock synthesizer is a low-jitter DLL that
generates a 278.528/311.04 MHz clock for the CMI
encoder. It is also used in both the receive and
transmit sides for clock and data recovery.
This 2x line rate clock is also available at the
TXCKxP/N pins for downstream synchronization or
system debug.
Transmit Backplane Equalizer
An optional fixed LVPECL equalizer is integrated in
the transmit path for architectures that use LIUs on
active interface cards.
compensate for up to 1.5m of FR4 trace and can be
enabled by the TXOUT1 pin or TXEQ bit as follows:
Transmit Loss of Lock
In transmit modes using the integrated CDR, the
78P2352 will declare a loss of lock condition when
there is no valid signal detected at the SIxDP/N data
inputs.
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TXOUT1 pin
Low
Float
Note: To avoid reflections causing unwanted
board noise, it’s recommended to power-down
unused transmit ports that are not terminated
with cable to an Rx input port.
Note: The Tx LOL indicator is invalid and
undefined when the parallel (nibble) interface is
selected.
coaxial
notes
cable
The CMI driver, encoder and
TXEQ bit
for
through
1
0
The fixed equalizer can
schematic
a
1:1
Tx Equalizer

and
Disabled
Enabled
2006 Teridian Semiconductor Corporation
wideband
layout
SOxCKP/N
POx[3:0]D
SIxCKP/N
SOxDP/N
PIx[3:0]D
PTOxCK
SIxDP/N
POxCK
POWER-DOWN FUNCTION
Power-down controls are provided to allow the
78P2352 to be shut off.
power-down can be set independently through SW
control. Total power-down is achieved by powering
down both the transmitter and receiver.
In HW mode, both transmitters can also be globally
powered down using the TXPD control pin.
LOOPBACK MODES
In SW mode, LLBKx and RLBKx bits in the Signal
Control Register are provided to activate the local
and remote loopback modes respectively.
In HW mode, the LPBKx pins can be used to
activate local and remote analog loopback modes as
shown in the table below.
PIxCK
LPBK pin
SOxCKP/N
Note: The serial interface and configuration
registers are not affected by power-down.
SIxCKP/N
POx[3:0]D
SOxDP/N
PIx[3:0]D
SIxDP/N
PTOxCK
POxCK
PIxCK
Float
High
Low
Lock Detect
Figure 7: Remote (Analog) Loopback
Tx CDR
Figure 6: Local (Analog) Loopback
Lock Detect
Tx CDR
Decoder
Analog Loopback Mode
Normal operation
Remote (analog) Loopback:
Recovered receive clock and data
looped back directly to the transmit
driver. The CMI decoder and most of
transmit path is bypassed.
Local (analog) Loopback:
Transmit clock and data looped back to
receiver at the analog media interface.
CMI
Decoder
CMI
PMOD, SMOD[1:0], PAR
FIFO
Lock Detect
Rx CDR
PMOD, SMOD[1:0], PAR
EACH CHANNEL: Tx
EACH CHANNEL: Rx
FIFO
Lock Detect
OC-3/ STM1-E/ E4 LIU
Rx CDR
EACH CHANNEL: Tx
EACH CHANNEL: Rx
CMI
Encoder
CMI
CMI
Transmit and receive
Encoder
CMI
Adaptive
Eq.
Dual Channel
Adaptive
LOS Detect
Eq.
LOS Detect
78P2352
RLBK
LLBK
RLBK
Rev. 2.4
LLBK
ECLxP/N
TXxCKP/N
CMIxP/N
RXxP/N
ECLxP/N
TXxCKP/N
CMIxP/N
RXxP/N