XR16C854CQ EXAR [Exar Corporation], XR16C854CQ Datasheet
XR16C854CQ
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XR16C854CQ Summary of contents
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JANUARY 2004 GENERAL DESCRIPTION 1 The XR16C854/854D (854 enhanced quad Universal Asynchronous Receiver and Transmitter (UART) each with 128 bytes of transmit and receive FIFOs, transmit and receive FIFO counters and trigger levels, automatic hardware and software flow ...
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XR16C854/854D 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO IGURE IN UT SSIGNMENT OR TXRDYD# 81 RXRDYD# 82 CDD# 83 RID# 84 RXD 85 VCC 86 INTSEL ...
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... ORDERING INFORMATION P N ART UMBER XR16C854CJ 68-Lead PLCC XR16C854IJ 68-Lead PLCC XR16C854CV 64-Lead TQFP XR16C854IV 64-Lead TQFP XR16C854DCV 64-Lead TQFP XR16C854DIV 64-Lead TQFP XR16C854CQ 100-Lead QFP XR16C854IQ 100-Lead QFP 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO PLCC ACKAGES N AND 60 DSRA# 10 DSRD# 59 ...
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XR16C854/854D 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO PIN DESCRIPTIONS Pin Description 64-TQFP 100-QFP 68-PLCC N AME DATA BUS INTERFACE ...
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REV. 3.0 Pin Description 64-TQFP 100-QFP 68-PLCC N AME CSD (N.C.) INTA 6 15 (IRQ#) INTB 12 21 INTC 37 49 INTD 43 55 (N.C.) INTSEL - 65 ...
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XR16C854/854D 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO Pin Description 64-TQFP 100-QFP 68-PLCC N AME RXRDY FSRS MODEM OR SERIAL I/O INTERFACE TXA 8 17 TXB 10 19 TXC ...
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REV. 3.0 Pin Description 64-TQFP 100-QFP 68-PLCC N AME CDA CDB CDC CDD RIA RIB RIC ...
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XR16C854/854D 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO Pin Description 64-TQFP 100-QFP 68-PLCC N AME N. Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain. Factory Test ...
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REV. 3.0 1.0 PRODUCT DESCRIPTION The XR16C854 (854) integrates the functions of 4 enhanced 16C550 Universal Asynchronous Receiver and Transmitter (UART). Each UART is independently controlled having its own set of device configuration registers. The configuration ...
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XR16C854/854D 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO 2.0 FUNCTIONAL DESCRIPTIONS 2.1 CPU Interface The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and write transactions. The 854 ...
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REV. 3.0 2.2 5-Volt Tolerant Inputs For devices that have top mark date code "F2 YYWW" and newer, the 854 can accept a voltage 5.5V on any of its inputs (except XTAL1) when ...
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XR16C854/854D 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO 2.6 Channels A-D Internal Registers Each UART channel in the 854 has a set of enhanced registers for control, monitoring and data loading and unloading. The configuration register set is compatible ...
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REV. 3 TXRDY# RXRDY# O ABLE AND FCR -0=0 BIT P INS (FIFO D ) ISABLED byte RXRDY data 0 = THR empty TXRDY byte in ...
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XR16C854/854D 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO IGURE AUD ATE ffer ABLE ...
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REV. 3 IGURE RANSMITTER PERATION IN NON Data Byte 16X Clock Transm it Shift Register (TSR) 2.11.3 Transmitter Operation in FIFO Mode The host may fill the transmit FIFO with up to ...
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XR16C854/854D 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO 2.12.1 Receive Holding Register (RHR) - Read-Only The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift Register. It provides the receive data ...
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REV. 3.0 2.13 Auto RTS Hardware Flow Control Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS# output is used to request remote unit to suspend/resume data ...
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XR16C854/854D 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO F 11. A RTS CTS F IGURE UTO AND LOW Local UART UARTA Receiver FIFO Trigger Reached Auto RTS Trigger Level Transmitter Auto CTS Monitor Assert RTS# to Begin Transmission 1 ...
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REV. 3.0 2.16 Auto Xon/Xoff (Software) Flow Control When software flow control is enabled characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) match the programmed values, the 854 will halt transmission as ...
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XR16C854/854D 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO The infrared encoder and decoder are enabled by setting MCR register bit ‘1’. When the infrared feature is enabled, the transmit data output, TX, idles at logic zero level. ...
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REV. 3.0 The 854 resumes normal operation by any of the following: a receive data start bit transition (logic data byte is loaded to the transmitter, THR or FIFO a change of ...
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XR16C854/854D 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO F 13 IGURE NTERNAL OOP Transmit Shift Register Receive Shift Register B C A-D ACK IN HANNELS VCC (THR/FIFO) MCR bit-4=1 (RHR/FIFO) VCC RTS# CTS# VCC DTR# DSR# OP1# ...
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REV. 3.0 3.0 UART INTERNAL REGISTERS Each UART channel in the 854 has its own set of configuration registers selected by address lines A0, A1 and A2 with a specific channel selected (See and Table 9. ...
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XR16C854/854D 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO . T 9: INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE RHR RD Bit ...
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REV. 3 INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE DLL RD/WR Bit DLM RD/WR Bit-7 0 ...
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XR16C854/854D 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO 4.0 INTERNAL REGISTER DESCRIPTIONS 4.1 Receive Holding Register (RHR) - Read- Only See “Receiver” on page 15. 4.2 Transmit Holding Register (THR) - Write-Only See “Transmitter” on page 14. 4.3 Interrupt ...
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REV. 3.0 IER[3]: Modem Status Interrupt Enable Logic 0 = Disable the modem status register interrupt (default). Logic 1 = Enable the modem status register interrupt. IER[4]: Sleep Mode Enable (requires EFR[ Logic 0 ...
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XR16C854/854D 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO ] T ABLE P ISR R RIORITY EGISTER EVEL ...
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REV. 3.0 FCR[2]: TX FIFO Reset This bit is only active when FCR bit ‘1’. Logic transmit FIFO reset (default). Logic 1 = Reset the transmit FIFO pointers and FIFO level ...
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XR16C854/854D 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO T 11: T ABLE RANSMIT AND FCTR FCTR FCR FCR FCR ...
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REV. 3.0 LCR[3]: TX and RX Parity Select Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data integrity check. See Table 12 for ...
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XR16C854/854D 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO 4.7 Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs. MCR[0]: DTR# Output The ...
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REV. 3.0 MCR[6]: Infrared Encoder/Decoder Enable Logic 0 = Enable the standard modem receive and transmit input/output interface (default). Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. The TX/RX output/input are routed to the ...
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XR16C854/854D 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO LSR[6]: THR and TSR Empty Flag This bit is set to a logic 1 whenever the transmitter goes idle set to logic 0 whenever either the THR or TSR ...
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REV. 3.0 MSR[7]: CD Input Status CD# (active high, logical 1). Normally this bit is the compliment of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the MCR register. The ...
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XR16C854/854D 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO EMSR[5:4]: Extended RTS Hysteresis EMSR EMSR[7:6]: Reserved 4.12 FIFO Level Register (FLVL) ...
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REV. 3.0 4.17 FIFO Data Count Register (FC) - Read-Only This register is accessible when LCR = 0xBF. Note that this register is not identical to the FIFO Level Count Register which is located in the ...
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XR16C854/854D 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO EFR[3:0]: Software Flow Control Select Single character and dual sequential characters software flow control is supported. Combinations of software flow control can be selected by programming these bits. T ABLE EFR ...
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REV. 3.0 EFR[6]: Auto RTS Flow Control Enable RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is selected, an interrupt will be generated when the ...
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XR16C854/854D 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO T 18: UART RESET CONDITIONS FOR CHANNELS A-D ABLE REGISTERS DLL DLM RHR THR IER FCR ISR LCR MCR LSR MSR SPR EMSR FLVL TRG FC FCTR EFR XON1 XON2 XOFF1 ...
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REV. 3.0 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation TYPICAL PACKAGE THERMAL RESISTANCE DATA (M Thermal Resistance (64-TQFP) Thermal Resistance (68-PLCC) Thermal Resistance (100-QFP) DC ...
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XR16C854/854D 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO AC ELECTRICAL CHARACTERISTICS TA (-40 + FOR INDUSTRIAL GRADE PACKAGE S P YMBOL ARAMETER CLK Clock Pulse Duration OSC Oscillator Frequency OSC ...
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REV. 3.0 AC ELECTRICAL CHARACTERISTICS TA (-40 + FOR INDUSTRIAL GRADE PACKAGE S P YMBOL ARAMETER TSI Delay From Stop To Interrupt TINT Delay From Initial INT ...
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XR16C854/854D 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO F 16 IGURE ODE NTEL ATA A0-A7 Valid Address T AS CS# IOR# T RDV D0- IGURE ODE NTEL ...
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REV. 3 IGURE ODE OTOROLA A0-A7 Valid Address T ADS CS# T RWS R/W# T RDA D0- IGURE ODE OTOROLA A0-A7 Valid ...
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XR16C854/854D 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO F 20 & I IGURE ECEIVE EADY NTERRUPT RX Start D0:D7 Bit INT RXRDY# IOR# (Reading data out of RHR & I IGURE RANSMIT EADY ...
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REV. 3 & I IGURE ECEIVE EADY NTERRUPT Start Bit RX S D0:D7 S D0:D7 Stop Bit INT T SSR RXRDY# First Byte is Received in RX FIFO IOR# (Reading data out ...
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XR16C854/854D 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO F 24 & I IGURE RANSMIT EADY NTERRUPT Start TX FIFO Bit Empty TX D0:D7 S (Unloading) IER[1] ISR is read enabled INT* TX FIFO fills up to trigger ...
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REV. 3.0 PACKAGE DIMENSIONS 64 LEAD THIN QUAD FLAT PACK ( 1.4 mm TQFP eating Plane Note: The control dimension is the millimeter column SYMBOL ...
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XR16C854/854D 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO 68 LEAD PLASTIC LEADED CHIP CARRIER (PLCC Note: The control dimension is the inch column SYMBOL ...
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REV. 3.0 100 LEAD PLASTIC QUAD FLAT PACK ( QFP, 1.95 mm Form) 81 100 Seating Plane A 1 Note: The control dimension is the millimeter column SYMBOL A ...
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XR16C854/854D 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO REVISION HISTORY Date Revision November 1999 Rev 1.0 Removed Preliminary designation. February 2002 Rev 2.0 Changed to standard style format. Text descriptions were clarified and sim- plified (eg. DMA operation, FIFO ...
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GENERAL DESCRIPTION................................................................................................. 1 F .................................................................................................................................................. 1 EATURES A ............................................................................................................................................. 1 PPLICATIONS F 1. XR16C854 B D .................................................................................................................................................. 1 IGURE LOCK IAGRAM 100- IGURE IN UT SSIGNMENT ...
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XR16C854/XR16C854D 3.3V AND 5V QUAD UART WITH 128-BYTE FIFO REV. 2.0 4 RANSMIT OLDING EGISTER 4 NTERRUPT NABLE EGISTER 4.3.1 IER versus Receive FIFO Interrupt Mode Operation................................................................................ 26 4.3.2 IER versus Receive/Transmit FIFO Polled ...