XR16C854CQ EXAR [Exar Corporation], XR16C854CQ Datasheet - Page 27

• Manufacturer Part Number: XR16C854CQ
• Description: 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
• Manufacturer: EXAR [Exar Corporation]

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REV. 3.0
IER[3]: Modem Status Interrupt Enable
IER[4]: Sleep Mode Enable (requires EFR[4] = 1)
IER[5]: Xoff Interrupt Enable (requires EFR[4]=1)0
IER[6]: RTS# Output Interrupt Enable (requires EFR[4]=1)
IER[7]: CTS# Input Interrupt Enable (requires EFR[4]=1)
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be
serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt
Source Table,
associated with each of these interrupt levels.
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4.4
4.4.1
4.4.2
Logic 0 = Disable the modem status register interrupt (default).
Logic 1 = Enable the modem status register interrupt.
Logic 0 = Disable Sleep Mode (default).
Logic 1 = Enable Sleep Mode.
Logic 0 = Disable the software flow control, receive Xoff interrupt (default).
Logic 1 = Enable the software flow control, receive Xoff interrupt. See Software Flow Control section for
details.
Logic 0 = Disable the RTS# interrupt (default).
Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# pin makes a transition
from low to high.
Logic 0 = Disable the CTS# interrupt (default).
Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition from
low to high.
LSR is by any of the LSR bits 1, 2, 3 and 4.
RXRDY is by RX trigger level.
RXRDY Time-out is by a 4-char plus 12 bits delay timer.
TXRDY is by TX trigger level or TX FIFO empty (or transmitter empty in auto RS-485 control).
MSR is by any of the MSR bits 0, 1, 2 and 3.
Receive Xoff/Special character is by detection of a Xoff or Special character.
CTS# is when its transmitter toggles the input pin (from low to high) during auto CTS flow control.
RTS# is when its receiver toggles the output pin (from low to high) during auto RTS flow control.
LSR interrupt is cleared by a read to the LSR register.
RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
RXRDY Time-out interrupt is cleared by reading RHR.
TXRDY interrupt is cleared by a read to the ISR register or writing to THR.
MSR interrupt is cleared by a read to the MSR register.
Xoff interrupt is cleared by a read to ISR or when Xon character(s) is received.
Special character interrupt is cleared by a read to ISR or after the next character is received.
RTS# and CTS# flow control interrupts are cleared by a read to the MSR register.
Interrupt Status Register (ISR) - Read-Only
Interrupt Generation:
Interrupt Clearing:
Table
10, shows the data values (bit 0-5) for the interrupt priority levels and the interrupt sources
See “Sleep Mode with Auto Wake-Up” on page 20.
27
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
XR16C854/854D