PT7A6632J PERICOM [Pericom Semiconductor Corporation], PT7A6632J Datasheet
PT7A6632J
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PT7A6632J Summary of contents
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Features • Provides full-duplex HDLC/SDLC channels • Compatible with 1.544 Mb/s T1 and 2.048Mb/s CEPT PCM-30 carrier format • Provides on-board buffer memory management • Supports standard hyperchannel configuration and fully programmable hyperchannel configuration • Provides ...
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Features ....................................................................................................................................................... 1 Applications ................................................................................................................................................ 1 Introduction ................................................................................................................................................. 1 Block Diagram ............................................................................................................................................ 4 Pin Information ........................................................................................................................................... 4 Pin Assignment .................................................................................................................................. 4 Pin Configuration .............................................................................................................................. 5 Pin Description .................................................................................................................................. 6 Functional Description ................................................................................................................................ 9 General Description ........................................................................................................................... 9 Transmit Bit-Level ...
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External Memory Organization and Definition ......................................................................................... 20 General Structure ............................................................................................................................. 20 Activation Memory .......................................................................................................................... 21 Channel Activation Byte ........................................................................................................ 21 Channel Buffer Pointers ......................................................................................................... 21 Data Processing Memory ................................................................................................................. 24 General ................................................................................................................................... 24 Transmit Data Buffer .............................................................................................................. 24 Transmit ...
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Block Diagram Figure 2. Block Diagram of PT7A6632 16 A0-A15 8 D0-D7 READ WRITE AS DMND ATTN ATACK SYSACC INTR RESET Pin Information Pin Assignment Table 1. Pin Assignment ...
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Pin Configuration Figure 3. Pin Configuration 10 CH1 11 CH2 12 CH3 13 CH4 14 Rx/Tx 15 TCLK 16 SYSCLK 17 TSER GND 20 GND ...
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Pin Description Table 2. Pin Description ...
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Table 2. Pin Description (Continued ...
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Table 2. Pin Description (Continued ...
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Functional Description General Description The PT7A6632 HDLC Controller is applied between an exter- nal memory and T1/E1 trunk interface to perform data trans- mission and reception. See Figure 1. Its signal attributes are shown in Figure 4. PT7A6632 reads ...
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Transmit Bit-Level Processor The block diagram of the Transmit Bit-Level Processor is shown in Figure 5. The external memory stores data to be trans- mitted and the channel operation modes in a set of linked buffers (referred as Transmit ...
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Figure 7. Transmit Frame Synchronization Timing - T1 Mode, SIS = 1 Channel 24 Bit 7 TCLK TMAX FILL/MASK* TSEREN (Low) TSER Data TSEREN (High) Data TSER * The F-bit time is processed as if the FILL/MASK = 0. ...
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Figure 9. Transmit Frame Synchronization Timing - T1 Mode, SIS = 0 Channel 24 Bit 7 Bit 8 TCLK TMAX FILL/MASK* TSEREN (Low) TSER Data TSEREN (High) Data TSER * The F-bit time is processed as if the FILL/MASK ...
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Hyperchannel Three standard ISDN hyperchannel options (two for T1, one for CEPT PCM-30) are available by setting HCS0 and HCS1 as well as T1/CEPT pins. See Table 3 and Figure 11. Table 3. Hyperchannel Selection ...
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Tri-State Serial Data Output TSER The TSER can be set to different state by setting TSEREN pin and FILL/MASK byte in the transmit command buffer. See Table 4. Table 4. Output Selection on TSER ...
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Receive Bit-Level Processor The block diagram of the Receive Bit-Level Processor is shown in Figure 12. The receive bit-level processor accept serial data from the T1/E1 trunk interface, perform HDLC deformat (pro- cesses flags, abort, deletes zeroes, checks FCS, ...
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HDLC Mode In HDLC mode, the Receive Processor detects flags, abort, delete zero-bit, check the Frame Check Sequences (FCS), and filters the time-fill bits by applying FILL/MASK byte to the received data. Reset the device will make all ...
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Figure 15. Receive Frame Synchronization Timing - CEPT PCM-30 Mode, SIS = 1 RRED RSYNC Proving Period 1 ( one full multiframe) RCLK RSER Bit 7 Bit 8 RRED RSYNC Time-slot 31, last frame of a multiframe Figure 16. ...
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Figure 17. Receive Frame Synchronization Timing - CEPT PCM-30 Mode, SIS = 0 RRED RSYNC Proving Period 1 ( one full multiframe) RCLK RSER Bit 6 Bit 7 Bit 8 RRED RSYNC Time-slot 31, last frame of a multiframe ...
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Memory Manager The Memory Manager controls data flow between Transmit Processor/Receive Processor and the external memory as shown in Figure 18. CPU assigns the external memory into several parts for activation information (Activation Memory) and data processing information (Data ...
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External Memory Organization and Definition General Structure The external memory is divided by the CPU into two func- tional blocks for channel activation and data processing, re- ferred as Activation Memory and Data Processing Memory. The Activation Memory contains ...
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Activation Memory The Activation Memory map is shown in the Figure 21. Channel Activation Byte The Channel Activation Byte are illustrated in the following table 5. The PT7A6632 reads this byte so that gets the channel number, the channel ...
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Figure 21b. Activation Memory Map Locations (MDFS = LOW) (Address) (HEX Active x XX00 XX01 ~ ~ XX7F XX80 Transmit Channel 0 Start Address (Low-Order Byte) XX81 Transmit Channel 0 Start Address (High-Order Byte) XX82 Transmit Channel ...
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Figure 22. Organization and Linking of Data or Command Buffers Address i i+7 i+7 i+7+k m m+7 m+7 m+7+n p p+7 p+7 p+7+r * Formats are different for Data buffer and Command buffer, ...
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Data Processing Memory General The Data Processing Memory refers to Data or Command buff- ers which are linked each other. The PT7A6632 accesses the Data Processing Memory for transmit/receive data and opera- tion commands. Each buffer has following configuration ...
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Table 6. Descriptors in Transmit Data Buffer ...
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Transmit Command Buffer The Transmit Command Buffer contains 8 bytes of descriptors and 2 bytes of Channel Mode & Rate Definition Data (and maybe the Hyperchannel Configuring Bytes) as shown in Figure 24. The MDFS pin decides the MS ...
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Descriptors The first 8 bytes in the Transmit Command Buffer are Descriptors that specify Next Buffer Address, Data Length and Status respectively. See Table 7 for the definition. Table 7. Descriptors in Transmit Command Buffer ...
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MODE Byte (Channel Mode) The MODE byte is set up by the CPU to specify channel modes of HDLC, non-HDLC signaling, non-HDLC data, loop, non- loop, inversion or non-inversion. The details are shown in Table 8. Table 8. ...
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FILL/MASK Byte (Rate Definition) The FILL/MASK byte is used as a masking pattern on the HDLC-formatted (including FLAG, header, data, CRC, and ABORT code) or non-HDLC-formatted data in order to adapt subrates that are multiples of 8kb/s to ...
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Flexible Hyperchannel Configuring Byte (Optional) The byte follows the FILL/MASK byte if any used to configure flexible hyperchannel. Bits specify number of a channel to be grouped into or removed from a hyperchannel. ...
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Receive Data Buffer The Receive Data Buffer contains 8 bytes of descriptors and j bytes of user’s data as shown in Figure 26. The MDFS pin decides the MS byte and LS byte locations (in even and odd addresses). ...
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Table 11. Descriptors in Receive Data Buffer ...
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Receive Command Buffer The Receive Command Buffer contains 8 bytes of descriptors and 2 bytes of Channel Mode & Rate Definition Data (and maybe Hyperchannel Configuring Bytes) as shown in Figure 27. The MDFS pin decides the MS byte ...
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Descriptors The first 8 bytes in the Receive Command Buffer is Descriptors that specifies Next Buffer Address, Data Length and Status respectively. See Table 12 for the definition. Table 12. Descriptors in Receive Command Buffer ...
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MODE Byte (Channel Mode) The Channel Mode Byte is set up by the CPU to specify channel modes of HDLC, non-HDLC signaling, non-HDLC data, loop, non-loop, inversion or non-inversion. The details are shown in Table 13. Table 13. ...
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Table 14. Receive Buffer Data Arrangement for Non-HDLC Bit-Oriented Signaling Channel ...
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FILL/MASK Byte (Rate Definition) The PT7A6632 FILL/MASK byte is used as a masking pattern on the HDLC-formatted (including FLAG, header, data, CRC, and ABORT code) or non-HDLC-formatted data in order to adapt subrates that are multiples of 8kb/s ...
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Device Operation Device Initialization The device is initialized by RESET signal. Upon reset, all the channels are set in the following states: - the operation mode is HDLC, inversion, non-loop, - FILL/MASK byte: 0000 0000, - all channels are ...
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Data Transmission and Reception Operation In transmission, the PT7A6632 reads the first command buffer according to the channel start address, judges status of buffer, fetches the MODE and FILL/MASK information for the chan- nel, then it reads the Next ...
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Figure 30. Typical Linked Buffer Receive Activity Activation Memory xx00 xxC0 Rx CH0 xxC1 xxC2 Rx CH1 xxC3 xxFE Rx CH31 xxFF Next BF Addr. Command Modes FILL/MASK Command Buffer PT019(05/02) PT7A6632 32-Channel HDLC Controller 1: ATTN goes high. ...
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Channel Period for Memory Access The PT7A6632 accesses the external memory for buffer man- agement and data processing. Normally, the T1/CEPT PCM-30 data flow requires that a byte of data should be supplied for transmission and a byte of ...
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Memory Address Memory Address Extension The output of CH0 - CH4 and Rx/Tx of the PT7A6632 can be used as upper address bits to extend the 16-bit addresses to 22- bit addresses. See an example in Figure 32. Or ...
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Memory Address Restrictions Activation Memory Address -- The PT7A6632 judges the channel start address for its invalidity immediately after it reads the Activation Memory for the address in response to the ATTN assertion. If the 16-bit address is found ...
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Figure 35. PT7A6632 External Memory Example Interface Waveforms - Single Write Memory Access SYSCLK DMND AS A0-A15 WRITE INTR* D0-D7 Rx/Tx CH0-CH4 * Activated by status write only. Figure 36. PT7A6632 External Memory Example Interface Waveforms - Double Write ...
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Figure 37. PT7A6632 External Memory Example Interface Waveforms - Single Read Memory Access SYSCLK DMND AS A0-A15 READ D0-D7 Rx/Tx CH0-CH4 Figure 38. PT7A6632 External Memory Example Interface Waveforms - Read Write Double Memory Access SYSCLK DMND AS A0-A15 ...
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Figure 39. PT7A6632 External Memory Example Interface Waveforms - Write Read Double Memory Access SYSCLK DMND AS A0-A15 READ WRITE D0-D7 INTR* Rx/Tx CH0-CH4 Figure 40. PT7A6632 External Memory Example Interface Waveforms - Single Activation Read Memory Access SYSCLK ...
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Figure 41. PT7A6632 External Memory Example Interface Waveforms - Single Write Memory Access Plus a Single Activation Read Access SYSCLK DMND AS A0-A15 WRITE INTR* D0-D7 Rx/Tx CH0-CH4 READ SYSACC * Activated by status write only. Figure 42. PT7A6632 ...
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Figure 43. PT7A6632 External Memory Example Interface Waveforms - Write/Read Double Memory Access Plus a Single Activation Read Access SYSCLK DMND AS A0-A15 READ WRITE D0-D7 INTR* Rx/Tx CH0-CH4 SYSACC * Activated by status write only. Detailed Specifications Absolute ...
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DC Electrical, Power Supply and Capacitance Characteristics Table 17. DC Electrical, Power Supply and Capacitance Characteristics ...
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AC Characteristics (Note: All output AC timing measurements are referenced to the 0.4V for low level and 2.4V for high level, and all input AC timing measurements are referenced to the 0.8V for low level and 2.0V for high ...
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Clock Timing Table 19. Clock Timing ...
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TCLK - RCLK Timing Table 20. TCLK - RCLK Timing ...
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PT7A6632 Receive Frame Synchronization Timing Table 29. Receive Frame Synchronization Timing ...
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External Memory Interface • Read Cycle Timing Table 22. Read Cycle Timing ...
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Write Cycle Timing Table 23. Write Cycle Timing ...
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Channel Activation/Deactivation Table 24. Channel Activation/Deactivation Timing ...
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Input Characteristics Table 25. Input Characteristics ...
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Output Characteristics Table 26. Output Characteristics ...
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Mechanical Specifications Figure 51. 68-Pin PLCC PT019(05/02) PT7A6632 32-Channel HDLC Controller 59 Data Sheet Ver:2 ...
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Ordering Information Table 27. Ordering Information ...
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Email: support@pti.com.cn China: No. 20 Building, 3/F, 481 Guiping Road, Shanghai, 200233, China Tel: (86)-21-6485 0576 Asia Pacific: Unit 1517, 15/F, Chevalier Commercial Centre, 8 Wang Hoi Rd, Kowloon Bay, Hongkong Tel: (852)-2243 3660 U.S.A.: 2380 Bering Drive, San ...