PT7A6632J PERICOM [Pericom Semiconductor Corporation], PT7A6632J Datasheet - Page 14

• Manufacturer Part Number: PT7A6632J
• Description: PT7A6632 32-Channel HDLC Controller
• Manufacturer: PERICOM [Pericom Semiconductor Corporation]

Tri-State Serial Data Output TSER
The TSER can be set to different state by setting TSEREN pin
and FILL/MASK byte in the transmit command buffer. See
Table 4.
When TSEREN = 0, and FILL/MASK bit = 0, the TSER output
line is in high impedance. This feature allows to connect up to
eight PT7A6632 devices together to realize subrate TDM trans-
mission.
Channel Operation Modes
The transmit channels can be set in the following operation
modes by CPU in transmit command buffer. See MODE byte in
the transmit command buffer for details (Figure 24).
•
In HDLC mode, the Transmit Processor generates flags, abort
and idle code, inserts zero-bit, count the Frame Check Se-
quences (FCS) for the data.
In HDLC mode, it is programmable to attach a number of flags
to the end of HDLC frame as time-fill sequence. The number of
flags is specified in the transmit data buffer.
The PT7A6632 counts the intentionally inserted zeroes based
on HDLC format. These intentionally inserted zeroes may be
counted as intraframe time-fill bits. In this case, the programmed
flag number will be adjusted according to the counting result.
Reset the device will make all channels in HDLC mode.
•
In non-HDLC data mode, the data from memory directly trans-
mit on TSER.
In non-HDLC data channel mode (DMI mode 0 or 1), CF/P bit
of STATUS byte of allocated data buffer should be reset to
ensure uninterrupted data transmit.
PT019(05/02)
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Table 4. Output Selection on TSER
T
T
T
T
T
S
S
S
S
S
HDLC Mode
Non-HDLC Data Mode
E
E
E
E
E
0
0
R
R
R
1
1
R
R
E
E
E
E
E
N
N
N
N
N
F
F
F
F
F
L I
L I
L I
L I
L I
/ L
/ L
/ L
/ L
/ L
0
0
M
M
M
M
M
1
1
A
A
A
A
A
S
S
S
S
S
K
K
K
K
K
e S
e S
e S
i H
d n
h g
d n
d n
i -
a
a d
a d
m
O
O
O
O
O
1
a t
a t
p
u
u
u
u
u
d e
p t
p t
p t
p t
p t
n a
t u
t u
t u
t u
t u
e c
n o
n o
n o
n o
n o
u o
T
T
T
T
T
p t
S
S
S
S
S
E
E
E
E
E
t u
R
R
R
R
R
14
PT7A6632 32-Channel HDLC Controller
•
The non-HDLC signaling requires no special consideration in
transmit data processing.
In non-HDLC signaling mode, CF/P bit of STATUS byte of
allocated data buffer should be reset to ensure uninterrupted
data transmit. The PT7A6632 assumes that no more than 2
linked data buffers are allocated to the signaling channel by
the CPU. Details are shown in Section “External Memory Or-
ganization and Definition” and Tables 8 and 14.
•
When a transmit channel is specified in Loop Mode, the
PT7A6632 will send the data of this channel into an interme-
diate buffer in PT7A6632 in channel period while sends the
data to TSER output. The data then will be sent back to the
external memory via a receive channel in Loop Mode. Each
time only one transmit and one receive channel can be speci-
fied in Loop Mode. The transmit loop channel number and
receive loop channel number are not necessarily identical. The
Loop Mode does not support hyperchannel.
If only a transmit loop channel is defined without a receive
loop channel defined, the loop operation can not be performed.
Reset the device will delete all Loop Mode.
•
If a transmit channel is set in inversion mode, data including
flag, ABORT and FCS bits will be inverted bit by bit when
transmit processing. Device reset sets all channel in inversion
mode.
Data Transmission Order
The PT7A6632 transmits data bytes in the same time sequence
as they are arranged in ascending addresses in the external
buffers. For a certain channel, the data at byte address m is
transmitted first, the data at address m+1 is transmitted next,
and so on while the data bytes are in the same buffer. After the
data in a data buffer is exhausted, the PT7A6632 starts to trans-
mit the next byte from the next buffer whose address is speci-
fied in the current buffer. The transition to the next buffer is
transparent to the CPU while the flow of actual data is main-
tained. This natural sequence of data flow is maintained for
flexible hyperchannels, as well.
The PT7A6632 transmits the LSB (D0) of a data byte first;
then the next LSB second; and the MSB (D7) last. The only
exception is that the MSB of the HDLC FCS (CRC-CCITT) is
transmitted first; the LSB transmitted last.
Non-HDLC Signaling Mode
Loop Mode
Logical Inversion
Data Sheet
Ver:2