PT7A6632J PERICOM [Pericom Semiconductor Corporation], PT7A6632J Datasheet - Page 16

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PT7A6632J

Manufacturer Part Number
PT7A6632J
Description
PT7A6632 32-Channel HDLC Controller
Manufacturer
PERICOM [Pericom Semiconductor Corporation]
Datasheet

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In HDLC mode, the Receive Processor detects flags, abort,
delete zero-bit, check the Frame Check Sequences (FCS), and
filters the time-fill bits by applying FILL/MASK byte to the
received data.
Reset the device will make all channels in HDLC mode.
In this mode, received data are directly written into external
memory without deformating.
PT019(05/02)
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Figure 13. 32kb/s Subrate Operation - Single Receive Channel
Figure 14. Receive Frame Synchronization Timing - T1 Mode, SIS = 1
HDLC Mode
Non-HDLC Data Mode
RSYNC
RCLK
RRED
RSER
RSYNC
RRED
Channel 24, last
multiframe
T1/CEPT PCM-30 Serial Input
Bit 7
frame of a
Proving Period 1
multiframe)
A 1 B C D 1 1 1 E 1 F G H 1 1 1
( one full
TS m in Frame n+1
Bit 8
Bit F
Proving Period 2
multiframe)
(one full
Bit 1
MSB
A B C D E F G H
1 0 1 1 1 0 0 0
Channel 1, first frame of the next
multiframe
TS m in Frame n
Bit 2
16
Proving Period 3
PT7A6632 32-Channel HDLC Controller
In non-HDLC signaling mode, PT7A6632 detects the
multiframe alignment sequence. If the alignment sequence is
valid, the received data will be sent to the external memory; if
not, the data will not be sent to external memory until a valid
alignment sequence is detected. The loss of the multiframe
alignment will be reported to external memory. Any channel(s)
can be specified to receive bit-oriented signaling. This feature
is very useful in central office switching applications.
multiframe)
(one full
Non-HDLC Signaling Mode
Bit 3
LSB
Bit 4
FILL/MASK
multiframe)
Received Data
Assembled Data Byte
(One full
From this point, fully
multiframe synchronized
until RRED goes high
Bit 5
Bit 6
Bit 7
Data Sheet
Bit 8
Ver:2

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