SST89V564RD-33-I-PJ SST [Silicon Storage Technology, Inc], SST89V564RD-33-I-PJ Datasheet - Page 10

• Manufacturer Part Number: SST89V564RD-33-I-PJ
• Description: FlashFlex51 MCU
• Manufacturer: SST [Silicon Storage Technology, Inc]

Data Sheet
TABLE
©2003 Silicon Storage Technology, Inc.
ALE/PROG#
Symbol
1. I = Input; O = Output
2. It is not necessary to receive a 12V programming supply voltage during flash programming.
3.ALE loading issue: When ALE pin experiences higher loading (>30pf) during the reset, the MCU may accidentally enter into modes
4. For 6 clock mode, ALE is emitted at 1/3 of crystal frequency.
PSEN#
XTAL1
XTAL2
P3[2]
P3[3]
P3[4]
P3[5]
P3[6]
P3[7]
RST
EA#
V
V
NC
other than normal working mode. The solution is to add a pull-up resistor of 3-50 KΩ to V
DD
SS
2-1: P
IN
Type
D
I/O
I/O
I/O
O
O
O
I
I
I
I
I
I
I
I
I
ESCRIPTIONS
1
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Name and Functions
INT0#: External Interrupt 0 Input
INT1#: External Interrupt 1 Input
T0: External count input to Timer/Counter 0
T1: External count input to Timer/Counter 1
WR#: External Data Memory Write strobe
RD#: External Data Memory Read strobe
Program Store Enable: PSEN# is the Read strobe to external program. When the device is
executing from internal program memory, PSEN# is inactive (High). When the device is exe-
cuting code from external program memory, PSEN# is activated twice each machine cycle,
except that two PSEN# activations are skipped during each access to external data memory.
A forced high-to-low input transition on the PSEN# pin while the RST input is continually held
high for more than 10 machine cycles will cause the device to enter external host mode pro-
gramming.
Reset: While the oscillator is running, a “high” logic state on this pin for two machine cycles
will reset the device. If the PSEN# pin is driven by a high-to-low input transition while the RST
input pin is held “high,” the device will enter the external host mode, otherwise the device will
enter the normal operation mode.
External Access Enable: EA# must be connected to V
fetch code from the external program memory. EA# must be strapped to V
gram execution. However, Security lock level 4 will disable EA#, and program execution is
only possible from internal program memory. The EA# pin can tolerate a high voltage
(See Section 13.0, “Electrical Specification”)
Address Latch Enable: ALE is the output signal for latching the low byte of the address dur-
ing an access to external memory. This pin is also the programming pulse input (PROG#) for
flash programming. Normally the ALE
quency
each access to external data memory. However, if AO is set to 1, ALE is disabled.
(See “Auxiliary Register (AUXR)” in Section 3.6, “Special Function Registers”)
No Connect
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator
circuits.
Crystal 2: Output from the inverting oscillator amplifier.
Power Supply
Ground
(C
4
ONTINUED
and can be used for external timing and clocking. One ALE pulse is skipped during
) (2
OF
2)
10
3
is emitted at a constant rate of 1/6 the crystal fre-
DD
, e.g. for ALE pin.
SS
in order to enable the device to
FlashFlex51 MCU
DD
S71207-04-000
for internal pro-
2
T2-1.4 1207
of 12V.
12/03