SST89V564RD-33-I-PJ SST [Silicon Storage Technology, Inc], SST89V564RD-33-I-PJ Datasheet - Page 64

• Manufacturer Part Number: SST89V564RD-33-I-PJ
• Description: FlashFlex51 MCU
• Manufacturer: SST [Silicon Storage Technology, Inc]

Data Sheet
12.0 SYSTEM CLOCK AND CLOCK OPTIONS
12.1 Clock Input Options and Recom-
mended Capacitor Values for Oscillator
Shown in Figure 12-1 are the input and output of an inter-
nal inverting amplifier (XTAL1, XTAL2), which can be con-
figured for use as an on-chip oscillator.
When driving the device from an external clock source,
XTAL2 should be left disconnected and XTAL1 should be
driven.
At start-up, the external oscillator may encounter a higher
capacitive load at XTAL1 due to interaction between the
amplifier and its feedback capacitance. However, the
capacitance will not exceed 15 pF once the external signal
meets the V
Crystal manufacturer, supply voltage, and other factors
may cause circuit performance to differ from one applica-
tion to another. C1 and C2 should be adjusted appropri-
ately for each design. Table 12-1, shows the typical values
for C1 and C2 vs. crystal type for various frequencies
TABLE 12-1:R
TABLE 12-2: C
©2003 Silicon Storage Technology, Inc.
Device
SST89E564RD/554RC
SST89V564RD/554RC
FIGURE 12-1: O
Ceramic
Crystal
Quartz
IL
and V
C2
ECOMMENDED
LOCK
IH
BY
specifications.
SCILLATOR
C
D
RYSTAL
Machine Cycle
OUBLING
Using the On-Chip Oscillator
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Clocks per
C 1
C 2
12
12
V
ALUES FOR
T
C
YPE
F
HARACTERISTICS
EATURES
Standard Mode (x1)
C1 = C2
20-30pF
40-50pF
Max. External Clock Frequency
C1
XTAL2
XTAL1
V
T12-1.1 1207
SS
AND
(MHz)
40
33
64
More specific information about on-chip oscillator design
can be found in the FlashFlex51 Oscillator Circuit Design
Considerations application note.
12.2 Clock Doubling Option
By default, the device runs at 12 clocks per machine cycle
(x1 mode). The device has a clock doubling option to
speed up to 6 clocks per machine cycle. Please refer to
Table 12-2 for detail.
Clock double mode can be enabled either via the external
host mode or the IAP mode. Please refer to Table 4-1 and
Table 4-2 for the external host mode enabling command
and to Tables 4-6 and 4-7 for the IAP mode enabling com-
mand (When set, the EDC# bit in SFST register will indi-
cate 6 clock mode.).
The clock double mode is only for doubling the inter-
nal system clock and the internal flash memory, i.e.
EA#=1. To access the external memory and the peripheral
devices, careful consideration must be taken. Also note
that the crystal output (XTAL2) will not be doubled.
External Clock Drive
Oscillator
External
Signal
Machine Cycle
Clocks per
NC
6
6
Clock Double Mode (x2)
XTAL2
XTAL1
V
SS
Max. External Clock Frequency
1207 F21.1
FlashFlex51 MCU
(MHz)
S71207-04-000
20
16
T12-2.3 1207
12/03