NS16C2552TVA NSC [National Semiconductor], NS16C2552TVA Datasheet - Page 23

• Manufacturer Part Number: NS16C2552TVA
• Description: Dual UART with 16-byte/64-byte FIFOs and up to 5 Mbit/s Data Rate
• Manufacturer: NSC [National Semiconductor]

Bit
7:0
7:0
Bit
6.0 Register Set
6.10 SCRATCHPAD REGISTER (SCR)
This 8-bit Read/Write Register does not control the serial
channel in any way. It is intended as a Scratchpad Register
to be used by the programmer to hold data temporarily.
6.11 PROGRAMMABLE BAUD GENERATOR
The NS16C2552 contains two independently programmable
Baud Generators. Each is capable of taking prescaler input
and dividing it by any divisor from 1 to 2
highest input clock frequency recommended with a divisor =
1 is 80MHz. The output frequency of the Baud Generator is
16 X the baud rate, [divisor # = (frequency input) / (baud rate
Table 17 provides decimal divisors to use with crystal fre-
quencies of 1.8432 MHz, 3.072 MHz and 18.432 MHz. For
baud rates of 38400 and below, the error obtained is mini-
Note: For baud rates of 250k, 300k, 375k, 500k, 750k and 1.5M using a
7:0
Bit
Output Data
Baud Rate
115,200
19,200
38,400
24MHz crystal causes minimal error.
1200
2400
4800
9600
150
300
600
50
75
DLM Data
Bit Name
Bit Name
DLL Data
SCR Data
Bit Name
Output 16x Clock
TABLE 17. Baud Rate Generation Using 1.8432 MHz Clock with MCR[7]=0
0xXX
Divider (dec)
0xXX
R/W
R/W
R/W
R/W
Def
Def
2304
1536
(Continued)
768
384
192
96
48
24
12
6
3
1
0xFF
R/W
R/W
Def
Divisor Latch MSB
This 8-bit register holds the most significant byte of the 16-bit baud rate generator divisor.
Note: This register value does not change upon MR reset.
Divisor Latch LSB
This 8-bit register holds the least significant byte of the 16-bit baud rate generator divisor.
Note: This register value does not change upon MR reset.
TABLE 16. DLM (0x1, LCR[7] = 1, LCR != 0xBF)
TABLE 15. DLL (0x0, LCR[7] = 1, LCR != 0xBF)
16
-1 (Figure 1). The
Scratchpad Register
This 8-bit register does not control the UART in any way. It is intended as a
scratchpad register to be used by the programmer to hold temporary data.
User 16x Clock
Divisor (hex)
TABLE 14. SCR (0x7)
900
600
300
180
C0
0C
60
30
18
06
03
01
23
X 16)]. The output of each Baud Generator drives the trans-
mitter and receiver sections of the associated serial channel.
Two 8-bit latches per channel store the divisor in a 16-bit
binary format. These Divisor Latches must be loaded during
initialization to ensure proper operation of the Baud Genera-
tor. Upon loading either of the Divisor Latches, a 16-bit Baud
Counter is loaded.
mal. The accuracy of the desired baud rate is dependent on
the crystal frequency chosen. Using a divisor of zero is not
recommended.
DLM Program
Value (hex)
Description
Description
09
06
03
01
00
00
00
00
00
00
00
00
Description
DLL Program
Value (hex)
C0
0C
00
00
00
80
60
30
18
06
03
01
Data Rate
Error (%)
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0
0
0
0
0
0
0
0
0
0
0
0