EN5367QI ENPIRION [Enpirion, Inc.], EN5367QI Datasheet - Page 13
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EN5367QI
Manufacturer Part Number
EN5367QI
Description
6A Synchronous Highly Integrated DC-DC PowerSoC
Manufacturer
ENPIRION [Enpirion, Inc.]
Datasheet
1.EN5367QI.pdf
(22 pages)
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Functional Description
Synchronous Buck Converter
The EN5367QI is a synchronous, programmable
power supply with integrated power MOSFET
switches and integrated inductor. The nominal input
voltage range is 2.5V to 5.5V. The output voltage is
programmed using an external resistor divider
network. The control loop is voltage-mode with a
type III compensation network. Much of the
compensation circuitry is internal to the device.
However, a phase lead capacitor is required along
with the output voltage feedback resistor divider to
complete the type III compensation network. The
device uses a low-noise PWM topology. Up to 6A
of continuous output current can be drawn from this
converter. The 4 MHz switching frequency allows
the use of small size input / output capacitors, and
realizes a wide loop bandwidth within a small foot
print.
Protection Features:
The power supply has the following protection
features:
•
•
•
Additional Features:
•
•
•
Power Up-Down Sequencing
During power-up, ENABLE should not be asserted
before PVIN, and PVIN should not be asserted
before AVIN. Tying all three pins together meets
these requirements. ENABLE can also be tied to
AVIN and come up with it, while PVIN can be safely
ramped up and down. Alternatively, PVIN can be
brought high after AVIN is asserted, and the device
can be turned on and off by toggling the ENABLE
pin.
Enable Operation
The ENABLE pin provides a means to enable
normal operation or to shut down the device. A
logic high will enable the converter into normal
operation. When the ENABLE pin is asserted (high)
the device will undergo a normal soft start. A logic
low will disable the converter. A logic low will power
down the device in a controlled manner and the
device is subsequently shut down. The ENABLE
©Enpirion 2012 all rights reserved, E&OE
07013
Over-Current Protection
Thermal Shutdown with Hysteresis.
Under-voltage Lockout
Frequency Synchronization (External Clock)
Programmable Soft-start
Output Enable and Power OK
Enpirion Confidential
October 25, 2012
signal has to be low for at least the ENABLE Lock-
out Time (2.4ms) in order for the device to respond
to a falling edge on this pin. Note that the device
should not be enabled into a pre-biased output.
Pre-Bias Operation
The EN5367QI is not designed to be turned on into
a pre-biased output voltage. Be sure the output
capacitors are not charged or the output of the
EN5367QI is not pre-biased when the EN5367QI is
first enabled.
Frequency Synchronization
The switching frequency of the DC/DC converter
can be phase-locked to an external clock source to
move unwanted beat frequencies out of band. To
avail this feature, the clock source should be
connected to the SYNC pin. An activity detector
recognizes the presence of an external clock signal
and automatically phase-locks the internal oscillator
to this external clock. Phase-lock will occur as long
as the input clock frequency is in the lock range
specified in the Electrical Characteristics Table.
If the SYNC function is not to be used, this pin has
to be grounded. Do not float this pin or tie it to a
static high voltage.
Spread Spectrum Mode
The external clock frequency may be swept within
the SYNC frequency lock range at repetition rates
of up to 10 kHz in order to reduce EMI frequency
components.
Soft-Start Operation
During Soft-start, the output voltage is ramped up
gradually upon start-up. The output rise time is
controlled by the choice of soft-start capacitor,
which is placed between the SS pin (30) and the
AGND pin (32).
where rise time is in ms, and C
start-up of the converter, the reference voltage to
the error amplifier is linearly increased to its final
level by an internal current source of approximately
10uA. Typical soft-start rise time is ~3.75ms with a
soft-start capacitor of 47nF. The rise time is
measured from when V
voltage crosses its logic high threshold, to when
V
OUT
Rise Time [ms]: T
reaches its programmed value.
R
IN
≈ (C
www.enpirion.com, Page 13
> V
ss
UVLOR
[nF]* 0.08) ± 25%
SS
and ENABLE pin
is in nF. During
EN5367QI
Rev: C