CDK2307AILP64X CADEKA [Cadeka Microcircuits LLC.], CDK2307AILP64X Datasheet

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CDK2307AILP64X

Manufacturer Part Number
CDK2307AILP64X
Description
Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters
Manufacturer
CADEKA [Cadeka Microcircuits LLC.]
Datasheet
Data Sheet
CDK2307
Dual, 20/40/65/80MSPS, 12/13-bit
Analog-to-Digital Converters
Ordering Information (QFN-6 Package)
Moisture sensitivity level for all parts is MSL-2A.
©2009 CADEKA Microcircuits LLC
Part Number
CDK2307AILP64
CDK2307AILP64X
CDK2307BILP64
CDK2307BILP64X
CDK2307CILP64
CDK2307CILP64X
CDK2307DILP64
CDK2307DILP64X
F E A T U R E S
n
n
n
n
n
n
n
n
n
n
n
A P P L I C A T I O N S
n
n
n
n
n
n
n
13-bit resolution
20/40/65/80MSPS maximum sampling rate
Ultra-low power dissipation: 30/55/85/102mW
SNR 72dB at 80MSPS and 8MHz F
Internal reference circuitry
1.8V core supply voltage
1.7V – 3.6V I/O supply voltage
Parallel CMOS output
64-pin QFN package
(TQFP-64 package option also available)
Dual channel
Pin compatible with CDK2308
Handheld Communication, PMR, SDR
Medical Imaging
Portable Test Equipment
Digital Oscilloscopes
Baseband / IF Communication
Video Digitizing
CCD Digitizing
Speed
20MSPS
20MSPS
40MSPS
40MSPS
65MSPS
65MSPS
80MSPS
80MSPS
IN
Package
QFN-64
QFN-64
QFN-64
QFN-64
QFN-64
QFN-64
QFN-64
QFN-64
General Description
The CDK2307 is a high performance, low power dual Analog-to-Digital Con-
verter (ADC). The ADC employs internal reference circuitry, a CMOS control
interface and CMOS output data, and is based on a proprietary structure.
Digital error correction is employed to ensure no missing codes in the com-
plete full scale range.
Several idle modes with fast startup times exist. Each channel can be inde-
pendently powered down and the entire chip can either be put in Standby
Mode or Power Down mode. The different modes are optimized to allow the
user to select the mode resulting in the smallest possible energy consumption
during idle mode and startup.
The CDK2307 has a highly linear THA optimized for frequencies up to 70MHz.
The differential clock interface is optimized for low jitter clock sources and
supports LVDS, LVPECL, sine wave and CMOS clock inputs.
Functional Block Diagram
Pb-Free
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
RoHS Compliant
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Operating Temperature Range
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
A m p l i fy t h e H u m a n E x p e r i e n c e
CLK_EXT
Packaging Method
Tray
Tape & Reel
Tray
Tape & Reel
Tray
Tape & Reel
Tray
Tape & Reel
www.cadeka.com

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CDK2307AILP64X Summary of contents

Page 1

... Portable Test Equipment n Digital Oscilloscopes n Baseband / IF Communication n Video Digitizing n CCD Digitizing n Ordering Information (QFN-6 Package) Part Number Speed Package CDK2307AILP64 20MSPS QFN-64 CDK2307AILP64X 20MSPS QFN-64 CDK2307BILP64 40MSPS QFN-64 CDK2307BILP64X 40MSPS QFN-64 CDK2307CILP64 65MSPS QFN-64 CDK2307CILP64X 65MSPS QFN-64 CDK2307DILP64 80MSPS QFN-64 CDK2307DILP64X ...

Page 2

Data Sheet Ordering Information (TQFP-64 Package) Part Number Speed Package CDK2307AITQ64 20MSPS TQFP-64 CDK2307AITQ64X 20MSPS TQFP-64 CDK2307BITQ64 40MSPS TQFP-64 CDK2307BITQ64X 40MSPS TQFP-64 CDK2307CITQ64 65MSPS TQFP-64 CDK2307CITQ64X 65MSPS TQFP-64 CDK2307DITQ64 80MSPS TQFP-64 CDK2307DITQ64X 80MSPS TQFP-64 Moisture sensitivity level for all parts ...

Page 3

Data Sheet Pin Assignments (Continued) Pin No. Pin Name Description 19 CLK_EXT_EN CLK_EXT signal enabled when low (zero). Tristate when high. 20 DFRMT Data format selection. 0: Offset Binary, 1: Two's Complement 21 PD_N Full chip Power Down mode when ...

Page 4

Data Sheet Absolute Maximum Ratings The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper ...

Page 5

Data Sheet Electrical Characteristics (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20/40/65/80MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Parameter DC Accuracy No Missing Codes Offset Error ...

Page 6

Data Sheet Electrical Characteristics - CDK2307A (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Parameter Performance SNR Signal to Noise ...

Page 7

Data Sheet Electrical Characteristics - CDK2307B (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 40MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Parameter Performance SNR Signal to Noise ...

Page 8

Data Sheet Electrical Characteristics - CDK2307C (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 65MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Parameter Performance SNR Signal to Noise ...

Page 9

Data Sheet Electrical Characteristics - CDK2307D (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 80MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Parameter Performance SNR Signal to Noise ...

Page 10

Data Sheet Digital and Timing Electrical Characteristics (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 50 MSPS clock, 50% clock duty cycle, -1 dBFS input signal, 5pF capacitive load, unless otherwise noted) Symbol Parameter Clock Inputs ...

Page 11

Data Sheet CLK_EXT Recommended Usage Analog Input The analog input to the CDK2307 is done through a switched capacitor track-and-hold amplifier optimized for differential operation. Operation at mid supply common mode voltage is recommended even if performance will be good ...

Page 12

Data Sheet and that the bandwidth of the transformer is appropriate. The bandwidth should exceed the sampling rate of the ADC with at least a factor of 10 also important to keep phase mismatch between the differential ADC ...

Page 13

Data Sheet The quality of the input clock is extremely important for high-speed, high-resolution ADCs. The contribution to SNR from clock jitter with a full scale signal at a given frequency is shown in equation 1. SNR = 20 log ...

Page 14

Data Sheet Table 1: Data Format Description for 2V Differential Input Voltage (IPx - INx) 1.0 V +0.24mV -0.24mV -1.0V Reference Voltages The reference voltages are internally generated and buff- ered based on a bandgap voltage reference. No external decoupling ...

Page 15

Data Sheet Mechanical Dimensions QFN-64 Package aaa 0.05 Dia. R 1.14 bbb 1.14 TOP VIEW D2 Pin 1 ID 0.45 0. BOTTOM VIEW ©2009 CADEKA Microcircuits ...

Page 16

Data Sheet Mechanical Dimensions (Continued) TQFP-64 Package TOP VIEW DETAIL SIDE VIEW For additional information regarding our products, please visit CADEKA at: CADEKA Headquarters Loveland, Colorado T: 970.663.5452 T: 877.663.5452 (toll free) CADEKA, the CADEKA logo design, COMLINEAR and the ...

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