CDK2307AILP64X CADEKA [Cadeka Microcircuits LLC.], CDK2307AILP64X Datasheet - Page 12

• Manufacturer Part Number: CDK2307AILP64X
• Description: Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters
• Manufacturer: CADEKA [Cadeka Microcircuits LLC.]

Data Sheet
and that the bandwidth of the transformer is appropriate.
The bandwidth should exceed the sampling rate of the
ADC with at least a factor of 10. It is also important to
keep phase mismatch between the differential ADC inputs
small for good HD2 performance. This type of transformer
coupled input is the preferred configuration for high fre-
quency signals as most differential amplifiers do not have
adequate performance at high frequencies. Magnetic
coupling between the transformers and PCB traces may
impact channel crosstalk, and must hence be taken into
account during PCB layout.
If the input signal is traveling a long physical distance
from the signal source to the transformer (for example a
long cable), kick-backs from the ADC will also travel along
this distance. If these kick-backs are not terminated prop-
erly at the source side, they are reflected and will add to
the input signal at the ADC input. This could reduce the
ADC performance. To avoid this effect, the source must
effectively terminate the ADC kick-backs, or the traveling
distance should be very short. If this problem could not be
avoided, the circuit in Figure 6 can be used.
Figure 5 shows AC-coupling using capacitors. Resistors
from the CM_EXT output, RCM, should be used to bias the
differential input signals to the correct voltage. The series
capacitor, CI, form the high-pass pole with these resistors,
and the values must therefore be determined based on
the requirement to the high-pass cut-off frequency.
©2009 CADEKA Microcircuits LLC
Figure 4. Transformer-Coupled Input
Figure 5. AC-Coupled Input
47
R
T
pF
33
33
Note that startup time from Sleep Mode and Power Down
Mode will be affected by this filter as the time required
to charge the series capacitors is dependent on the filter
cut-off frequency.
If the input signal has a long traveling distance, and the
kick-backs from the ADC not are effectively terminated
at the signal source, the input network of Figure 6 can
be used. The configuration is designed to attenuate the
kickback from the ADC and to provide an input impedance
that looks as resistive as possible for frequencies below
Nyquist. Values of the series inductor will however depend
on board design and conversion rate. In some instances
a shunt capacitor in parallel with the termination resistor
(e.g. 33pF) may improve ADC performance further. This
capacitor attenuate the ADC kick-back even more, and
minimize the energy traveling towards the source. How-
ever, the impedance match seen into the transformer will
become worse.
Clock Input And Jitter Considerations
Typically high-speed ADCs use both clock edges to generate
internal timing signals. In the CDK2307 only the rising
edge of the clock is used. Hence, input clock duty cycles
between 20% and 80% are acceptable.
The input clock can be supplied in a variety of formats.
The clock pins are AC-coupled internally, and hence a
wide common mode voltage range is accepted. Differ-
ential clock sources such as LVDS, LVPECL or differential
sine wave can be connected directly to the input pins.
For CMOS inputs, the CLKN pin should be connected to
ground, and the CMOS clock signal should be connected
to CLKP. For differential sine wave clock input the ampli-
tude must be at least ±800mV
1:1
Figure 6. Alternative Input Network
optional
R
68
T
120nH
120nH
220
33
33
pp
.
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pF
12