ADUM1310ARWZ-RL1 AD [Analog Devices], ADUM1310ARWZ-RL1 Datasheet - Page 4

• Manufacturer Part Number: ADUM1310ARWZ-RL1
• Description: Triple-Channel Digital Isolators
• Manufacturer: AD [Analog Devices]

ADuM1310/ADuM1311
1
2
3
4
5
6
7
8
9
10
11
Parameter
All voltages are relative to their respective ground.
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
t
measured from the 50% level of the rising edge of the V
t
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
CM
that can be sustained while maintaining V
magnitude is the range over which the common mode is slewed.
Input enable time is the duration from when V
transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the
much shorter duration, as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when V
until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL
the same orientation as Channel A must be included to account for the total current consumed.
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section.
See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through
Figure 12 for total V
within the recommended operating conditions.
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
PHL
PSK
I
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information
DDx (Q)
For All Models
H
propagation delay is measured from the 50% level of the falling edge of the V
is the magnitude of the worst-case difference in t
is the maximum common-mode voltage slew rate that can be sustained while maintaining V
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient
Common-Mode Transient
Refresh Rate
Input Enable Time
Input Disable Time
Input Supply Current per Channel,
Output Supply Current per
Input Dynamic Supply Current
Output Dynamic Supply Current
is the quiescent current drawn from the corresponding supply by a single channel. To calculate the total quiescent current, an additional inaccessible channel in
Immunity at Logic High
Output
Immunity at Logic Low Output
Quiescent
Channel, Quiescent
per Channel
per Channel
8
DD1
10
and V
11
11
9
9
DD2
10
supply currents as a function of data rate for ADuM1310/ADuM1311 channel configurations.
O
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
DISABLE
Symbol
t
|CM
|CM
f
t
t
I
I
I
I
DDI (Q)
DDO (Q)
DDI (D)
DDO (D)
r
R
ENABLE
DISABLE
is set low until the output states are guaranteed to match the input states in the absence of any input data logic
/t
PHL
F
H
L
or t
Ix
|
|
signal to the 50% level of the rising edge of the V
PLH
that is measured between units at the same operating temperature, supply voltages, and output load
Min
25
25
Rev. F | Page 4 of 20
Ix
signal to the 50% level of the falling edge of the V
Typ
2.5
35
35
1.2
0.50
0.38
0.12
0.04
O
> 0.8 V
Max
2.0
5.0
0.73
0.53
DD2
Ox
2
. CM
signal.
logic state (see Table 12).
L
is the maximum common-mode voltage slew rate
Unit
ns
kV/μs
kV/μs
Mbps
μs
μs
mA
mA
mA/
Mbps
mA/
Mbps
Test Conditions
C
V
transient magnitude = 800 V
V
transient magnitude = 800 V
V
V
L
Ix
Ix
IA
IA
= 15 pF, CMOS signal levels
, V
, V
= V
= 0 V, V
IB
IB
Ox
, V
, V
DD1
signal. t
IC
IC
/V
CM
= 0 V or V
= 0 V or V
DD2
= 1000 V,
PLH
, V
CM
propagation delay is
DISABLE
= 1000 V,
DD1
DD1
is set high