OX16PCI954-TQC60-A OXFORD [Oxford Semiconductor], OX16PCI954-TQC60-A Datasheet - Page 10
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OX16PCI954-TQC60-A
Manufacturer Part Number
OX16PCI954-TQC60-A
Description
Integrated Quad UART and PCI interface
Manufacturer
OXFORD [Oxford Semiconductor]
Datasheet
1.OX16PCI954-TQC60-A.pdf
(72 pages)
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Parallel port
32-bit Local bus
Data Sheet Revision 1.3
local
8-bit
See
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
bus
00
OXFORD SEMICONDUCTOR LTD.
122
121
120
108
119
118
107
106
105
Bus
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
01
Mode
47-55, 58-61, 66-68,
80-87, 92-95,98-101
76-9, 105-8, 118-
10
114-7
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
122
123
102
109
112
113
121
11
Dir
OD
OD
OD
OD
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Z
I
I
I
I
I
I
I
1
Name
ACK#
INTR#
PE
BUSY
WAIT#
SLIN#
ADDRSTB#
SLCT
ERR#
INIT#
INIT#
AFD#
DATASTB#
STB#
WRITE#
PD[7:0]
LBRST
LBRST#
LBDOUT
LBCLK
LBCS[3:0]#
LBDS[3:0]#
LBWR#
LBRDWR#
LBRD#
Hi-Z
LBA[12:0]
LBD[31:0]
Description
Acknowledge (SPP mode). ACK# is asserted (low) by the
peripheral to indicate that a successful data transfer has
taken place.
Identical function to ACK# (EPP mode).
Paper Empty. Activated by printer when it runs out of paper.
Busy (SPP mode). BUSY is asserted (high) by the peripheral
when it is not ready to accept data
Wait (EPP mode). Handshake signal for interlocked IEEE
1284 compliant EPP cycles.
Select (SPP mode). Asserted by host to select the peripheral
Address strobe (EPP mode) provides address read and write
strobe
Peripheral selected. Asserted by peripheral when selected.
Error. Held low by the peripheral during an error condition.
Initialize (SPP mode). Commands the peripheral to initialize.
Initialize (EPP mode). Identical function to SPP mode.
Auto Feed (SPP mode, open-drain)
Data strobe (EPP mode) provides data read and write strobe
Strobe (SPP mode). Used by peripheral to latch data
currently available on PD[7:0]
Write (EPP mode). Indicates a write cycle when low and a
read cycle when high
Parallel data bus
Local bus active-high reset
Local bus active-low reset
Local bus data out enable. This pin can be used by external
transceivers; it is high when LBD[7:0] are in output mode and
low when they are in input mode.
Buffered PCI clock. Can be enabled / disabled by software
Local bus active-low Chip-Select (Intel mode)
Local bus active-low Data-Strobe (Motorola mode)
Local Bus active-low write-strobe (Intel mode)
Local Bus Read-not-Write control (Motorola mode)
Local Bus active-low read-strobe (Intel mode)
Permanent high impedance (Motorola mode)
Local bus address signals
Local bus data signals
OX16PCI954
Page 10