OX16PCI952-TQAG OXFORD [Oxford Semiconductor], OX16PCI952-TQAG Datasheet
OX16PCI952-TQAG
Available stocks
Related parts for OX16PCI952-TQAG
OX16PCI952-TQAG Summary of contents
Page 1
... UART into enhanced modes or pre- configure the parallel port, prior to any PCI configuration accesses and before control is handed to generic device drivers. Microwire is a trade mark of National Semiconductor. TM External—Free Release TM TM © Oxford Semiconductor 2005 DS-0028 Jul 05 Part No. OX16PCI952-TQC60-A OX16PCI952-TQAG ...
Page 2
... OXFORD SEMICONDUCTOR LTD EVISION ISTORY REV DATE REASON FOR CHANGE / SUMMARY OF CHANGE Jul 2005 29/07/2005 Revision for additional order code DS-0028 Jul 05 External-Free Release OX16PCI952 Page 2 ...
Page 3
... OXFORD SEMICONDUCTOR LTD. C ONTENTS 1 PERFORMANCE COMPARISON.......................................................................................................... 5 1.1 IMPROVEMENTS OF THE OX16PCI952 OVER DISCRETE SOLUTIONS:...................................................................... 5 2 BLOCK DIAGRAM ................................................................................................................................ 7 3 PIN INFORMATION ............................................................................................................................... 8 4 PIN DESCRIPTION................................................................................................................................ 9 5 CONFIGURATION & OPERATION ..................................................................................................... 14 6 PCI TARGET CONTROLLER.............................................................................................................. 15 6.1 OPERATION ..................................................................................................................................................................... 15 6.2 CONFIGURATION SPACE ............................................................................................................................................... 16 6.3 ACCESSING FUNCTION 0 AND FUNCTION 1 ............................................................................................................... 18 6.4 ACCESSING THE LOCAL CONFIGURATION REGISTERS........................................................................................... 20 6 ...
Page 4
... OXFORD SEMICONDUCTOR LTD. DS-0028 Jul 05 External-Free Release OX16PCI952 Page 4 ...
Page 5
... Readable FIFO levels Clock prescaler options Rx/Tx disable Software reset Device ID 9-bit data frames RS485 buffer enable Infra-red (IrDA) Table 1: OX16PCI952 performance compared with PCI Bridge + generic UART/Parallel Port Combinations. 1.1 Improvements of the OX16PCI952 over discrete solutions: Higher degree of integration: The OX16PCI952 offers two ...
Page 6
... OXFORD SEMICONDUCTOR LTD. Power management: Both functions of the OX16PCI952 comply with the PCI Power Management Specification 1.0 and the PC98/99 Power Management specifications, by offering the extended capabilities for Power Management and supporting the power states D0, D2 and D3. This achieves significant power savings by allowing device drivers to power down the PCI functions and disable the UART channels and the parallel port ...
Page 7
... Clock & XTLI Baud Rate XTLO Generator EE_DO EE_CK EEPROM Interface EE_CS EE_DI DS-0028 Jul 05 Function 0 Interrupt Logic Function 1 Internal Data/Control Bus Figure 1: OX16PCI952 Block Diagram External-Free Release OX16PCI952 SOUT[1:0] SIN[1:0] RTS[1:0] Dual DTR[1:0] UARTs CTS[1:0] DSR[1:0] DCD[1:0] RI[1:0] MIO logic MIO[1:0] PD[7:0] ACK# ...
Page 8
... GND Z_PM E 120 AD31 AD30 AD29 AD28 AD27 AD26 AD25 GND 128 1 DS-0028 Jul 05 80 OX16PCI952 10 20 External-Free Release OX16PCI952 70 65 SEEPROM _CS 64 SEEPROM _DO SEEPROM _DI GND M ULTI ULTI IO 0 VDD GND M ODE0 TEST GND GND AD0 AD1 ...
Page 9
... EXT_DATA_IN[0] Serial data input, UART 0. EXT_DATA_IN[1] Serial data input, UART 1. IrDA_In[0] UART IrDA data inputs, for UART 0 and 1. IrDA_In[1] Serial data input pins redefined as IrDA data inputs when MCR[6] of the corresponding UART channel is set in enhanced mode External-Free Release OX16PCI952 Page 9 ...
Page 10
... Active-low modem “Ring-Indicator” input, for UART 0 and RI[1]# UART 1. Tx_Clk_In[0] External transmitter clock. Tx_Clk_In[0] The RI Uart pins are redefined as transmitter clk pins (and thus used indirectly by the receiver) when the UART channel’s CKS[6] register bit =’1’. External-Free Release OX16PCI952 Page 10 ...
Page 11
... Write signal in EPP mode. Indicates a write cycle when low and a read cycle when high. PD[7:0] Parallel port bi-directional data bus LOCAL_TRANS_EN Parallel Port Data Output Enable. This pin can be used by external transceivers high when PD[7:0] are in output mode, and low when they are in input mode. External-Free Release OX16PCI952 Page 11 ...
Page 12
... Dual UARTs and Function 1 is the parallel port. MODE0 = 1. Device operates only as a single function device, where function 0 is the Dual UARTs. Function 1 does not exist, so the parallel port is not visible accesses. V VDD Device Power G GND Device Gnd. Table 2: Pin Descriptions External-Free Release OX16PCI952 to PCI 2 Page 12 ...
Page 13
... RF radiation from the chip. Further precaution is taken by segmenting the GND and VDD rails to isolate the PCI and UART pins. DS-0028 Jul 05 P_I 5v PCI input P_I/O 5v PCI bi-directional P_O 5v PCI output P_OD 5v PCI open drain G Ground V 5.0V power External-Free Release OX16PCI952 Page 13 ...
Page 14
... OXFORD SEMICONDUCTOR LTD & O ONFIGURATION PERATION The OX16PCI952 is a multi-function, target-only PCI device, compliant with the PCI Local Bus Specification, Revision 2.2 and PCI Power Management Specification, Revision 1.0. The OX16PCI952 affords maximum configuration flexibility by treating the internal UARTs and the parallel port as separate logical functions (function 0 and function 1, respectively) ...
Page 15
... DEVSEL# bus signal two clocks after FRAME# is first sampled low on all bus transaction frames which address the chip. Fast back-to-back transactions (to both functions) are supported by the OX16PCI952 as a target bus master can perform faster sequences of write transactions (when an inter-frame turn-around cycle is not required) to the UARTs, the Parallel Port, the PCI configuration space and the local configuration registers ...
Page 16
... OXFORD SEMICONDUCTOR LTD. 6.2 Configuration space The OX16PCI952 is a dual-function (or single function) device, where each logical function has its own PCI configuration space. All the required fields in the predefined PCI header region have been implemented. The device dependant region of the PCI configuration space contains the PCI Power Management Extended Capability register set ...
Page 17
... Table 5: PCI configuration space Reset Values NOTE 1: Function 1 PCI Configuration Space is available only when the OX16PCI952 is operating in the dual-function device mode (MODE0 pin = ‘0’). Configuration accesses to Function 1 in the single function device mode (MODE0 pin = ‘1’) will result in ‘Master-Aborts’. ...
Page 18
... Note 1: Since 4K of memory space is reserved to map both UARTs and the full bus address is not used for decoding, there are a number of aliases of the UARTs in the allocated memory region External-Free Release OX16PCI952 Not Implemented PCI Offset from Base Address 4, for UART 0 UART 1 ...
Page 19
... Example: BAR0 = 0x00000379 (8 bytes of I/O at address 0x378) BAR1 = 0x00000779 (4 bytes of I/O at address 0x778) If this relationship is not used, custom drivers will be needed. DS-0028 Jul 05 . External-Free Release OX16PCI952 Page 19 ...
Page 20
... These bits define a time value for the internal powerdown filter, part of the power management circuitry of Function 0 (only). Once Function0 is ready to go into the power down mode, the OX16PCI952 will wait for the specified filter time and if Function0 is still indicating a power-down, it will assert a powerdown request and a PCI interrupt (if the latter is enabled) ...
Page 21
... PME# pin if this option has been enabled. A value of ‘0’ prevents MIO1 from setting the PCI PME_Status bit. This pin can affect function 0 or function 1, through the control defined in the GIS (local configuration) register. 31:6 Reserved DS-0028 Jul 05 EEPROM EEPROM External-Free Release OX16PCI952 Read/Write Reset PCI - ...
Page 22
... The location offset of the registers are such that the FIFO levels are usually read before the status registers so that the status of the N characters indicated in the receiver FIFO levels are valid. DS-0028 Jul 05 Read/Write EEPROM Read/Write EEPROM External-Free Release OX16PCI952 Reset PCI - R 0x00h - R ...
Page 23
... However, when the MIO 0 pin is routed to Function 1, then a powerdown state on the pin MIO 0 will immediately issue a powerdown request, for function 1, without any filters. DS-0028 Jul 05 Read/Write EEPROM . External-Free Release OX16PCI952 Reset PCI - R 0x0h - R 0x0h - ...
Page 24
... EEPROM. Note that even though the UART interrupts are enabled in this register, by default after a reset the IER registers of the individual UARTs are disabled so a PCI interrupt will not be asserted by any UART after a hardware reset. DS-0028 Jul External-Free Release OX16PCI952 ...
Page 25
... This is valid only when the device is operating in the dual-function mode. The 5 sources of interrupts on the OX16PCI952, can be enabled/disabled individually using the options in the local configuration register “GIS”. By default, the interrupt options for the UARTs and the parallel port are enabled in the GIS register ...
Page 26
... Note that the power-state of function 0 is only changed by the device driver and at no point will the OX16PCI952 change its own power state. The powerdown interrupt merely informs the device driver that this logical function is ready for power down ...
Page 27
... Note that the power-state of function 1 is only changed by the device driver and at no point will the OX16PCI952 change its own power state. The powerdown interrupt merely informs the device driver that this logical function is ready for power down ...
Page 28
... While PME_En (PMCSR[8]) remains set, the PME_Status will continue to assert the PME# pin to inform the device driver that a power management wake up event has occurred. After a wake up event is signalled, the device driver is expected to return this function to the D0 power- state External-Free Release OX16PCI952 Page 28 ...
Page 29
... I OX16C950 UART NTERNAL Each of the internal UARTs in the OX16PCI952 is an OX16C950 rev B specification high-performance serial port. The features of this UART are described in this section. 7.1 Operation – mode selection The UART is backward compatible with the 16C450, 16C550, 16C654 and 16C750 UARTs. The operation of the port depends on a number of mode settings, which are referred to throughout this section ...
Page 30
... TCR i.e. to set the device cycle sampling clock it would be necessary to write 0x0D to TCR. For further information see section 7.10.3 The UART also offers 9-bit data frames for multi-drop industrial applications. External-Free Release OX16PCI952 Page 30 ...
Page 31
... CTS Temporary data storage register and Indexed control register offset value bits Unused Divisor latch bits [7:0] (Least significant byte) Divisor latch bits [15:8] (Most significant byte) Table 9: Standard 550 Compatible Registers External-Free Release OX16PCI952 Bit 3 Bit 2 Bit 1 Bit 0 Modem Rx Stat THRE RxRDY ...
Page 32
... Detect Number of characters in the receiver FIFO Number of characters in the transmitter FIFO Data read/written depends on the value written to the SPR prior to the access of this register (see Table 11: 950 Specific Registers External-Free Release OX16PCI952 Bit 2 Bit 1 Bit 0 In-band flow control mode Bit 2 Bit 1 ...
Page 33
... Wakeup disable Disable FCR[6] FCR[5] FCR[4] Unused Force RxRdy Unused inactive Hardwired Port Index ( 0x00 ) Unused Table 12: Indexed Control Register Set External-Free Release OX16PCI952 Bit 3 Bit 2 Bit 1 Bit 0 Auto Tx Rx DSR Disable Disable Flow Control Enable 3 Bit “fractional” part of clock prescaler ...
Page 34
... Write the desired offset to SPR (address 111b). Read the desired value from ICR (address 101b). Write 0x00 offset to SPR to select ACR. Clear bit 6 of ACR bye writing x0xxxxxxb to ICR, thus enabling access to standard registers again. DS-0028 Jul 05 External-Free Release OX16PCI952 Page 34 ...
Page 35
... Table 13: Output Signal Reset State DS-0028 Jul 05 7.3.2 Software Reset An additional feature available in the OX16PCI952 UARTs is software resetting of the serial channel. This command has the same effect on a single channel as a hardware reset except it does not reset the clock source selections (i.e. CKS register and CKA register). To reset the UART write 0x00 to the Channel Software Reset register ‘ ...
Page 36
... FCR[5]=0: FIFO size is 16 bytes. FCR[5]=1: FIFO size is 128 bytes. In non-Enhanced mode and when FIFOSEL pin is low, FCR[5] is writable only when LCR[7] is set. Note that in Enhanced mode, the FIFO size is increased to 128 bytes when FCR[0] is set. External-Free Release OX16PCI952 112 Page 36 ...
Page 37
... Table 16: LCR Data Length Configuration LCR[2]: Number of stop bits LCR[2] defines the number of stop bits per serial character. LCR[2] Data length Table 17: LCR Stop Bit Number Configuration External-Free Release OX16PCI952 Mode Ext. 550 / 750 650 FIFO Size 128 FIFO Size 128 ...
Page 38
... Note that in 16C550 this bit is only cleared when all of the erroneous data are removed from the FIFO. In 9-bit data framing mode parity is permanently disabled, so this bit is not affected by LSR[2]. External-Free Release OX16PCI952 bit of the received data in RHR. Page 38 ...
Page 39
... This enable is only operative in Enhanced mode (EFR[4]=1). In non-Enhanced mode, RTS interrupt is permanently enabled IER[7]: CTS interrupt mask logic 0 ⇒ Disable the CTS interrupt. logic 1 ⇒ Enable the CTS interrupt. This enable is only operative in Enhanced mode (EFR[4]=1). In non-Enhanced mode, CTS interrupt is permanently enabled. External-Free Release OX16PCI952 Page 39 ...
Page 40
... A valid XOFF character is received while in-band flow control is enabled. • A received character matches XOFF2 while special character detection is enabled, i.e. EFR[5]=1. • A received character matches special character 9-bit mode (see section 7.11.9 cleared on an ISR read of a level 5 interrupt. External-Free Release OX16PCI952 Page 40 ...
Page 41
... XON-Any is disabled. logic 1 ⇒ XON-Any is enabled. In enhanced mode (EFR[4]=1), this bit enables the Xon- Any operation. When Xon-Any is enabled, any received data will be accepted as a valid XON (see in-band flow control, section 7.9.3). External-Free Release OX16PCI952 the Page 41 ...
Page 42
... UART in any way and can be used for temporary data storage. The register may also be used to define an offset value to access the registers in the Indexed Control Register set. For more information on Indexed Control registers see sections 7.2 and 7.11. External-Free Release OX16PCI952 Page 42 ...
Page 43
... EFR[4] = 1), where the RTS# pin will be forced inactive high if the RFL reaches the upper flow control threshold. This will be released when the RFL drops below the lower threshold. 650 and 950-mode drivers should use this bit to enable RTS flow control. External-Free Release OX16PCI952 Page 43 ...
Page 44
... MCR[1]=0 at any time. Automatic DTR/DSR flow control behaves in the same manner as RTS/CTS flow control but is enabled by ACR[3:2], regardless of whether or not the UART is in Enhanced mode. External-Free Release OX16PCI952 Page 44 ...
Page 45
... However, each UART of the OX16PCI952 is designed in a manner to enable it to accept other multiplications of the bit rate clock. It can use values from 4x to 16x clock as programmed in the TCR as long as the clock (oscillator) frequency error, stability and jitter are within reasonable parameters ...
Page 46
... OXFORD SEMICONDUCTOR LTD. values in bits-per-second (bps) that are obtained if the divisor latch = 0x01 and the Prescaler is set to 1. The OX16PCI952 has the facility to operate at baud-rates Mbps in normal mode. Table 26 indicates how the value in the register corresponds to the number of clock cycles per bit. TCR[3:0] is used to program the clock. TCR[7:4] are unused and will return “ ...
Page 47
... The driver software can determine if the remote transmitter is disabled by DTR# out-of-band flow control by reading this bit. In loopback mode this bit reflects the flow control status rather than the pin’s actual state. External-Free Release OX16PCI952 ...
Page 48
... In half-duplex systems using RS485 protocol, this facility enables the DTR# line to directly control the enable signal of external 3-state line driver buffers. When the transmitter is empty the DTR# would go inactive once the SOUT line returns to it’s idle marking state. External-Free Release OX16PCI952 Page 48 ...
Page 49
... EFR[7]. However, RTS# is automatically de-asserted and re-asserted when EFR[6] is set and RFL reaches FCH and drops below FCL. DSR# flow control is configured with ACR[2]. DTR# flow control is configured with ACR[4:3]. External-Free Release OX16PCI952 Page 49 ...
Page 50
... FIFO. In this case, as long as there are no errors pending, i.e. LSR[1], LSR[3], and LSR[4] are clear, '0' can be read back from LSR[7] and LSR[1], thus differentiating between an ‘address’ interrupt and receiver error or overrun interrupt in External-Free Release OX16PCI952 Page 50 ...
Page 51
... PME# line. MDM[7:6]: Reserved 7.11.11 Readable FCR ‘RFC’ The RFC register is located at offset 0x0F of the ICR This read-only register returns the current state of the FCR register (Note that FCR is write-only). This register is included for diagnostic purposes. External-Free Release OX16PCI952 Page 51 ...
Page 52
... The register is effectively an enhancement to the CKS register. This register is cleared to 0x00 after a hardware reset to maintain compatibility with 16C550, but is unaffected by software reset. This allows the user to select a clock mode and then reset the channel to work-around any timing glitches. External-Free Release OX16PCI952 Page 52 ...
Page 53
... I DIRECTIONAL ARALLEL 8.1 Operation and Mode selection The OX16PCI952 offers a compact, low power, IEEE-1284 compliant host-interface parallel port, designed to interface to many peripherals such as printers, scanners and external drives. It supports compatibility modes, SPP, NIBBLE, PS2, EPP and ECP modes. The register set is compatible with the Microsoft® register definition. ...
Page 54
... Parallel port interrupt The parallel port interrupt is asserted on function 1’s interrupt pin (INTA# by default, on the OX16PCI952). This interrupt is enabled by setting bit 4 of the DCR register. When the interrupt is enabled, a rising edge of the ACK# (INTR#) pin results in a parallel port interrupt to be asserted on function 1’ ...
Page 55
... EPP mode only: Timeout logic 0 ⇒ EPP Timer Timeout has not occurred. logic 1 ⇒ EPP Timer Timeout has occurred (Reading this bit clears it). Other Parallel Port modes: Unused This bit returns a ‘1’. External-Free Release OX16PCI952 Bit 3 Bit 2 Bit 1 Bit 0 ERR# INT# ...
Page 56
... DCR[7:6]: Reserved These bits are reserved and drivers must not utilise the values associated with these bits. The OX16PCI952 returns “00” for these bits, for all parallel port modes. 8.3.5 EPP address register ‘EPPA’ EPPA is located at offset 003h in lower block, and is only used in EPP mode ...
Page 57
... These bits define the operational mode of the parallel port. logic ‘000’ SPP logic ‘001’ PS2 logic ‘010’ Reserved logic ‘011’ ECR logic ‘100’ EPP logic ‘101’ Reserved logic ‘110’ Test logic ‘111’ Config External-Free Release OX16PCI952 Page 57 ...
Page 58
... S EEPROM S ERIAL PECIFICATION The OX16PCI952 can be configured using an optional serial electrically-erasable programmable read only memory (EEPROM). If the EEPROM is not present, the device will remain in its default configuration after reset. Although this may be adequate for some applications, many will benefit from the degree of programmability afforded by this feature ...
Page 59
... Zone 1: Function Access Zone 1 allows each UART and the Parallel Port of the OX16PCI952 to be pre-configured, prior to any PCI accesses. This is very useful when these functions need to run with (typically generic) device drivers and these drivers are not capable of utilising the enhanced features/modes of these logical units ...
Page 60
... These seven bits define the byte-offset of the PCI configuration register to be programmed. For example the byte-offset of the Interrupt Pin register is 0x3D. Offset values are tabulated in section 6.2. 7:0 8-bit value of the register to be programmed Table 28: Zone 4 data format (data) External-Free Release OX16PCI952 Page 60 ...
Page 61
... Class Code bits 23 to 16. 0x0E 7 Header Type (Multi/single function bit) 0x2E 7:0 Subsystem ID bits 0x2F 7:0 Subsystem ID bits 0x3D 7:0 Interrupt pin. 0x42 7:0 Power Management Capabilities bits 0x43 7:0 Power Management Capabilities bits Table 29: EEPROM-writable PCI configuration registers DS-0028 Jul 05 External-Free Release OX16PCI952 Page 61 ...
Page 62
... DC input voltage input current IN T Storage temperature STG Symbol Parameter V DC supply voltage DD T Temperature – Commercial C Table 31: Recommended operating conditions DS-0028 Jul 05 Table 30: Absolute maximum ratings External-Free Release OX16PCI952 Min Max Units -0.3 7 +/- 10 mA -40 125 °C Min Max Units 4 ...
Page 63
... Any Output Buffer Note 1 : This value depends upon the customer design. Note 2: This value excludes package parasitics Condition Min 4.75 -0 OUT mA, 6mA 2.4 OUT 5 External-Free Release OX16PCI952 Min Typ Max Units 2.0 V 0.8 V 1.4 V 2.0 V 0.8 V -10 10 μ 100 -10 10 μA ...
Page 64
... 0.015 CC 0.4V to 2.4V 1 2.4V to 0.4V 1 Table 32: Characteristics of PCI I/O buffers + 2.45) for 3.1 < V OUT OUT ) for 0.71 > V OUT OUT Table 33: Isochronous mode timing External-Free Release OX16PCI952 mA Eq. A -142 mA Eq. B 206 +1 -1 V/nS 5 V/nS ≤ > 0 Min Max Units TBD 10 ...
Page 65
... FRAME# AD[31:0] C/BE[3:0]# IRDY# TRDY# DEVSEL# STOP# Figure 2: PCI Write transaction to the PCI Configuration Space DS-0028 Jul Address Data Bus CMD Byte enable# (Function 0 or Function Address Data Bus CMD Byte enable# (Function 0 or Function 1) External-Free Release OX16PCI952 Page 65 ...
Page 66
... Figure 3. PCI read from the internal UARTs (UART 0 or UART 1) CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# TRDY# DEVSEL# STOP# Figure 4. PCI Write to the internal UARTs (UART0 or UART 1) DS-0028 Jul Address Data Bus CMD Byte enable# Wait Address Data Bus CMD Byte enable# External-Free Release OX16PCI952 5 Data transf er Page 66 ...
Page 67
... OXFORD SEMICONDUCTOR LTD. Tpd (PCI CLK to Valid Parallel Port Data ) : 16 ns max* * These values exclude the effects of external parasitic (board) capacitances. DS-0028 Jul 05 External-Free Release OX16PCI952 Page 67 ...
Page 68
... OXFORD SEMICONDUCTOR LTD. Tpc : PCI CLK to Valid Parallel Port Control lines. Tpc (Slin_N) : 16.0 ns max* Tpc (Stb_N) : 16.0 ns max* Tpc (Init_N) : 16.0 ns max* Tpc (Afd_N) : 16.0 ns max* * These values exclude the effects of external parasitic (board) capacitances. DS-0028 Jul 05 External-Free Release OX16PCI952 Page 68 ...
Page 69
... Example waveform has the parallel port filters disabled. An extra 2 PCI CLK cycles will be incurred in the response of the host to the peripheral’s BUSY line when the filters are enabled. * These values exclude the effects of external parasitic (board) capacitances. DS-0028 Jul 05 Write to EPP Data Register (EPP Write Data cycle) External-Free Release OX16PCI952 Page 69 ...
Page 70
... Example waveform has the parallel port filters disabled. An extra 2 PCI CLK cycles will be incurred in the response of the host to the peripheral’s BUSY line when the filters are enabled. * These values exclude the effects of external parasitic (board) capacitances. DS-0028 Jul 05 External-Free Release OX16PCI952 Page 70 ...
Page 71
... Example waveform has the parallel port filters disabled. An extra 2 PCI CLK cycles will be incurred in the response of the host to the peripheral’s BUSY line when the filters are enabled. * These values exclude the effects of external parasitic (board) capacitances. DS-0028 Jul 05 External-Free Release OX16PCI952 Page 71 ...
Page 72
... Example waveform has the parallel port filters disabled. An extra 2 PCI CLK cycles will be incurred in the response of the host to the peripheral’s BUSY line when the filters are enabled. * These values exclude the effects of external parasitic (board) capacitances. DS-0028 Jul 05 External-Free Release OX16PCI952 Page 72 ...
Page 73
... Example waveform has the parallel port filters disabled. An extra 2 PCI CLK cycles will be incurred in the response of the host to the peripheral’s BUSY line when the filters are enabled. * These values exclude the effects of external parasitic (board) capacitances. DS-0028 Jul 05 2 Consecutive Write Transactions to ECP DFIFO External-Free Release OX16PCI952 ECP forward transfer. st Page 73 ...
Page 74
... ECP Reverse Transfer Cycle duration is dependant upon the timing response of the peripheral’s ACK_N line and the parallel port filters.Example waveform has the parallel port filters disabled. An extra 2 PCI CLK cycles will be incurred in the response of the host to the peripheral’s ACK_N line when the filters are enabled. DS-0028 Jul 05 External-Free Release OX16PCI952 Page 74 ...
Page 75
... OXFORD SEMICONDUCTOR LTD ACKAGE NFORMATION DS-0028 Jul 05 External-Free Release OX16PCI952 Page 75 ...
Page 76
... OXFORD SEMICONDUCTOR LTD RDERING NFORMATION OX16PCI952-TQC60 - A Revision Package Type – 128 TQFP OX16PCI952- RoHS compliant Revision Package Type – 128 TQFP DS-0028 Jul 05 External-Free Release OX16PCI952 Page 76 ...
Page 77
... No responsibility is assumed by Oxford Semiconductor for its use, nor for infringement of patents or other rights of third parties. No part of this publication may be reproduced, or transmitted in any form or by any means without the prior consent of Oxford Semiconductor Ltd. Oxford Semiconductor’s terms and conditions of sale apply at all times. DS-0028 Jul 05 External-Free Release OX16PCI952 Page 77 ...