OX16PCI952-TQAG OXFORD [Oxford Semiconductor], OX16PCI952-TQAG Datasheet - Page 18

• Manufacturer Part Number: OX16PCI952-TQAG
• Description: Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface
• Manufacturer: OXFORD [Oxford Semiconductor]

6.3
Access to the internal UARTs and the Parallel Port is achieved (at addresses defined by the Base Address Registers in the PCI
configuration space) via standard I/O and memory mapping. These BARs are configured by the system to allocate blocks of I/O
and memory space to the logical functions, according to the size required by the function. The base addresses that have been
allocated can then be used to access the functions. The mapping of these BARs is shown inTable 6.
6.3.1
IO and memory space
BAR 0, BAR 1, and BAR 4 of function 0 are used to access
the internal UARTs through I/O and Memory transactions.
The function reserves 8-byte blocks of I/O space for each
UART (total of 16-bytes) and a 4K byte block of memory
space for both UARTs.
Once the I/O and/or the Memory access enable bits in the
Command register (of this function’s PCI configuration
space) are set, the internal UARTs can be accessed using
the mappings shown in the following tables.
DS-0028 Jul 05
Address
BAR
Address
UART 1
UART 0
OXFORD SEMICONDUCTOR LTD.
0
1
2
3
4
5
000
001
002
003
004
005
006
007
000
001
002
003
004
005
006
007
Base Address mapping for UART0 and UART 1 registers,
Accessing Function 0 and Function 1
PCI access to the internal UARTs
Internal UART 0 and UART 1 (Memory Mapped)
PCI Offset from Base Address 0 ,
PCI Offset from Base Address 1,
Internal UART 0 (I/O Mapped)
Internal UART 1 (I/O Mapped)
for I/O accesses.
for UART 0 in I/O space
for UART 1 in I/O space
Function 0
NOTE 1. Function 1 is only accessible in the Dual Function mode (MODE0 = ‘0’)
00
01
02
03
04
05
06
07
00
01
02
03
04
05
06
07
Table 6: Base Address Register definition
Local configuration registers (Memory Mapped)
Local configuration registers (I/O Mapped)
External-Free Release
Not Implemented
Function 1
Note 1:
UARTs and the full bus address is not used for decoding, there are a
number of aliases of the UARTs in the allocated memory region
Address
UART
000
001
002
003
004
005
006
007
Parallel Port Extended Registers (I/O Mapped)
Base Address mapping for UART 0 and UART1 registers,
Parallel Port Base Registers (I/O Mapped)
1
Since 4K of memory space is reserved to map both
UART0 and UART 1 in Memory space (hex)
PCI Offset from Base Address 4, for
UART 0
Not Implemented
for memory accesses
0C
1C
00
04
08
10
14
18
OX16PCI952
UART 1
2C
3C
20
24
28
30
34
38
Page 18