OX16PCI952-TQAG OXFORD [Oxford Semiconductor], OX16PCI952-TQAG Datasheet - Page 27

• Manufacturer Part Number: OX16PCI952-TQAG
• Description: Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface
• Manufacturer: OXFORD [Oxford Semiconductor]

The device driver can optionally assert/de-assert any of its
selected (design dependent) MIO pins to switch-off VCC,
disable other external clocks, or activate shut-down modes.
The device can only issue a wakeup request (a power
management event, PME#) if it is enabled by this function’s
PME_En bit, bit-8 of the PCI Power Management Register
PMCSR. PME# assertion, is immediate and does not use
the powerdown filter timer. It operates even if the
powerdown filter time is set to disabled.
Like powerdown, wakeup requests for function 0 can be
generated by up to 4 sources: by each of the internal
UARTs and either of the 2 Multi-purpose MIO pins (when
they are associated with function 0). The means to
generate wakeup events from these sources will have been
setup prior to placing this function into the powerdown
states D2 or D3 (including setting of the PME_En bit).
For the case of each UART, when the device (function 0) is
in the powerstate D3, only activity on the channel’s RI line
(the trailing edge of a pulse) will generate a wakeup event.
When the device (function 0) is in the power-state D2, then
wake-ups are configurable. In this case, a change in the
state of any modem line (which is enabled by a 16C950-
specific mask bit) or a change in the state of the serial input
line (again, if enabled by a 16C950-specific mask bit) can
issue a wake up request on the PME# pin. It is worth noting
that after a hardware reset all of these mask bits are
cleared to enable wake up assertion from all modem lines
and the SIN line when in the powerstate D2. As the wake
up operation from D2 requires at least one mask bit to be
enabled, the device driver can for example disable the
masks with the exception of the Ring Indicator, so only a
modem ring can wake up the computer. In the case for a
wake up request from the serial input line EXT_DATA_IN
(from the power state D2) then the clock for that channel is
turned on so serial data framing can be maintained.
For the case of the MIO pins (associated with function 0),
the state of the MIO pins that results in wakeup requests is
determined by the settings in the local configuration
register MIC. The wakeup behaviour for these pins, unlike
the UARTs, is not dependent upon the powerstates D2 or
D3. As soon as the correct logic is invoked then a power
management event (wakeup) is asserted.
When function 0 issues a wake up request, either from the
UARTs or the MIO pins, the PME_Status bit in this
function’s PCI power management registers (PMCSR[15])
will be set. This is a sticky bit which will only be cleared by
writing a ‘1’ to it. While PME_En (PMCSR[8]) remains set,
the PME_Status will continue to assert the PME# pin to
inform the device driver that a power management wake up
event has occurred. After a wake up event is signalled, the
DS-0028 Jul 05
OXFORD SEMICONDUCTOR LTD.
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device driver is expected to return this function to the D0
power-state.
6.6.2
Provided that the necessary controls have been set in the
device’s local configuration registers (MIC, and GIS), only
the 2 multi_purpose (MIO) pins can be programmed to
issue powerdown requests and/or ‘wakeup’ requests
(power management events), for function 1. The parallel
port is not capable of issuing a powerdown request or
power management events but can be placed in a low
power state through power management involving the MIO
pins.
When either or both of the MIO pins are associated with
function 1, then the state of the MIO pin(s) that issues a
powerdown request is controlled by the MIC register. This
state can be the same MIO state that asserts function 1’s
interrupt pin for normal functionality. The assertion of the
MIO pins will result in a function 1 powerdown request
being made immediately. Unlike the case when the MIO
pins are associated with function 0, there is no powerdown
filtering time associated with function 1.
The powerdown request can be issued on the function’s
interrupt pin, if this option is enabled. Alternatively, the
device driver can poll function 1’s powerdown status field in
the local configuration register GIS[23] to determine a
powerdown request.
Upon a power down interrupt, the device driver can change
the power-state of the device (function 1) as required. Note
that the power-state of function 1 is only changed by the
device driver and at no point will the OX16PCI952 change
its own power state. The powerdown interrupt merely
informs the device driver that this logical function is ready
for power down. Before placing the device into the lower
power states, the driver must provide the means for the
function to generate a ‘wakeup’ (power management)
event.
Whenever the device driver changes function 1’s power-
state to state D2 or D3, the device takes the following
actions:
•
•
•
However, access to the configuration space is still enabled.
Parallel Port placed in low power mode.
PCI interrupts are disabled regardless of the values
contained in the GIS registers.
Access to I/O or Memory BARs is disabled.
Power Management of Function 1
OX16PCI952
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