OX16PCI952-TQAG OXFORD [Oxford Semiconductor], OX16PCI952-TQAG Datasheet - Page 35
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OX16PCI952-TQAG
Manufacturer Part Number
OX16PCI952-TQAG
Description
Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface
Manufacturer
OXFORD [Oxford Semiconductor]
Datasheet
1.OX16PCI952-TQAG.pdf
(77 pages)
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7.3
7.3.1
After a hardware reset, all writable registers are reset to
0x00, with the following exceptions:
DLL, which is reset to 0x01.
CPR, which is reset to 0x20.
The state of read-only registers following a hardware reset
is as follows:
RHR[7:0]: Indeterminate
RFL[6:0]: 0000000
TFL[6:0]: 0000000
LSR[7:0]: 0x60 signifying that both the transmitter and the
MSR[3:0]: 0000
MSR[7:4]: Dependent on modem input lines DCD, RI,
ISR[7:0]:
ASR[7:0]: 1xx00000
RFC[7:0]: 00000000
GDS[7:0]: 00000001
DMS[7:0]: 00000010
CKA[7:0]: 00000000
The reset state of output signals are tabulated below:
DS-0028 Jul 05
OXFORD SEMICONDUCTOR LTD.
Reset Configuration
Signal
SOUT
RTS#
DTR#
Hardware Reset
Table 13: Output Signal Reset State
transmitter FIFO are empty
DSR and CTS respectively
0x01, i.e. no interrupts are pending
2
2
2
2
2
2
2
2
Inactive High
Inactive High
Inactive High
Reset state
External-Free Release
7.3.2
An additional feature available in the OX16PCI952 UARTs
is software resetting of the serial channel. This command
has the same effect on a single channel as a hardware
reset except it does not reset the clock source selections
(i.e. CKS register and CKA register). To reset the UART
write 0x00 to the Channel Software Reset register ‘CSR’.
Software Reset
OX16PCI952
Page 35