OX16PCI954-TQC60-A OXFORD [Oxford Semiconductor], OX16PCI954-TQC60-A Datasheet - Page 16

• Manufacturer Part Number: OX16PCI954-TQC60-A
• Description: Integrated Quad UART and PCI interface
• Manufacturer: OXFORD [Oxford Semiconductor]

6.3
Access to the UARTs, local bus and parallel port is achieved via standard I/O and memory mapping, at addresses defined by the
Base Address Registers (BARs) in configuration space. The BARs are configured by the system to allocate blocks of I/O and
memory space to the logical functions, according to the size required by the function. The addresses allocated can then be used
to access the functions. The mapping of these BARs is shown inTable 6.
6.3.1
IO and memory space
BAR 0 and BAR 1 of function 0 are used to access the
internal UARTs. The function reserves a 32-byte block of
I/O space and a 4K byte block of memory space. Once the
I/O access enable and Memory access enable bits in the
Command register (configuration space) are set, the
UARTs can be accessed following the mapping shown in
Table 7.
Note 1:
BAR
Data Sheet Revision 1.3
Address
Address
OXFORD SEMICONDUCTOR LTD.
0
1
2
3
4
5
UART
UART
(hex)
000
001
002
003
004
005
006
007
000
001
002
003
004
005
006
007
Table 7: PCI address map for internal UARTs
Accessing logical functions
Internal UARTs (memory mapped)
PCI access to internal UARTs
Since 4K of memory space is reserved and the full bus
address is not used for decoding, there are a number of
aliases of the UARTs in the allocated memory region
Internal UARTs (I/O mapped)
UART0
PCI Offset from Base Address 0 for
PCI Offset from Base Address 1 for
0C
1C
00
01
02
03
04
05
06
07
00
04
08
10
14
18
Function0 in Memory space (hex)
Function 0
Function0 in IO space (hex)
(I/O and memory)
UART1
0A
0B
0C
0D
0E
2C
3C
08
09
0F
20
24
28
30
34
38
UART2
4C
5C
10
11
12
13
14
15
16
17
40
44
48
50
54
58
Table 6: Base Address Register definition
Local configuration registers (memory mapped)
Local configuration registers (I/O mapped)
Function 1
Local bus
Local bus (I/O mapped)
Local bus (memory mapped)
UART3
1C
1D
6C
7C
18
19
1A
1B
1E
1F
60
64
68
70
74
78
Unused
Unused
6.3.2
When the local bus is enabled (Mode 00), access to the
bus works in similar fashion to the internal UARTs. The
function reserves a block of I/O space and a block of
memory space. The I/O block size is user definable in the
range of 4 to 256 bytes; the memory range is fixed at 4K
bytes.
I/O space
In order to minimise the usage of IO space, the block size
for BAR0 of Function1 is user definable in the range of 4 to
256 bytes. Having assigned the address range, the user
can define two adjacent address bits to decode up to four
chip selects internally. This facility allows glueless
implementation of the local bus connecting to four external
peripheral chips. The address range and the lower address
bit for chip-select decoding (Lower-Address-CS-Decode)
are defined in the Local Bus Configuration register (see
LT2[26:20] in section 6.4).
The 8-bit Local Bus has eight address lines (LBA[7:0])
which correspond to the maximum IO address space. If the
maximum allowable block size is allocated to the IO space
(i.e. 256 bytes), then as access in IO space is byte aligned,
LBA[7:0] equal PCI AD[7:0] respectively. When the user
selects an address range which is less than 256 bytes, the
corresponding upper address lines will be set to logic zero.
The region can be divided into four chip-select regions
when the user selects the second uppermost non-zero
address bit for chip-select decoding. For example if 32-
bytes of IO space are reserved, the local bus address lines
A[4:0] are active and the remaining address lines are set to
zero. To generate four chip-selects the user should select
A3 as the Lower-Address-CS-Decode. In this case A[4:3]
will be used internally to decode chip-selects, asserting
LBCS0# when the address offset is 00-07h, LBCS1# when
PCI access to 8-bit local bus
Parallel port
Parallel port base registers
Parallel port extended registers
OX16PCI954
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