ISPLSI2064VE-100LB100 LATTICE [Lattice Semiconductor], ISPLSI2064VE-100LB100 Datasheet
ISPLSI2064VE-100LB100
Related parts for ISPLSI2064VE-100LB100
ISPLSI2064VE-100LB100 Summary of contents
Page 1
Features • SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC — 2000 PLD Gates — 64 and 32 I/O Pin Versions, Four Dedicated Inputs — 64 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, ...
Page 2
Functional Block Diagram Figure 1. ispLSI 2064VE Functional Block Diagram (64-I/O and 32-I/O Versions) Input Bus Output Routing Pool (ORP) Megablock I I/O 2 I/O 3 I/O 4 I/O 5 Global Routing Pool ...
Page 3
Absolute Maximum Ratings Supply Voltage V cc ................................................... Input Voltage Applied ..................................... -0.5 to +5.6V Off-State Output Voltage Applied .................. -0.5 to +5.6V Storage Temperature ..................................... -65 to 150 C Case Temp. with Power Applied .................... -55 to 125 C ...
Page 4
Switching Test Conditions Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. Output Load Conditions (see Figure 2) TEST CONDITION A Active ...
Page 5
External Timing Parameters 3 TEST PARAMETER # COND Data Propagation Delay, 4PT Bypass, ORP Bypass pd1 t pd2 A 2 Data Propagation Delay Clock Frequency with Internal Feedback max f — 4 Clock Frequency ...
Page 6
External Timing Parameters 3 TEST PARAMETER # COND Data Propagation Delay, 4PT Bypass, ORP Bypass pd1 Data Propagation Delay pd2 Clock Frequency with Internal Feedback max f — 4 Clock Frequency ...
Page 7
Internal Timing Parameters 2 PARAMETER # Inputs t 20 Input Buffer Delay Dedicated Input Delay din GRP t 22 GRP Delay grp GLB Product Term Bypass Path Delay (Combinatorial) 4ptbpc Product ...
Page 8
Timing Model I/O Cell Ded. In #21 I/O Delay I/O Pin #20 (Input) #45 Reset Y0,1,2 GOE 0 Derivations of su, h and co from the Product Term Clock Logic + Reg ...
Page 9
Power Consumption Power consumption in the ispLSI 2064VE device de- pends on two primary factors: the speed at which the device is operating and the number of Product Terms Figure 3. Typical Device Power Consumption vs fmax I CC can ...
Page 10
Signal Descriptions Signal Name RESET Active Low (0) Reset pin resets all the registers in the device. GOE 0, GOE1 Global Output Enable input pins. Y0, Y1, Y2 Dedicated Clock Input – These clock inputs are connected to one ...
Page 11
Signal Locations ...
Page 12
Signal Configuration ispLSI 2064VE 100-Ball caBGA Signal Diagram 10 9 I/O I I/O I I/O I I/O I GOE F VCC 0 TCK/ ...
Page 13
Pin Configuration ispLSI 2064VE 100-Pin TQFP Pinout Diagram RESET 11 VCC ...
Page 14
Pin Configuration ispLSI 2064VE 44-Pin PLCC Pinout Diagram I/O 28 I/O 29 I/O 30 I/O 31 GOE1/Y0 VCC BSCAN TDI/IN 0 I/O 0 I/O 1 I/O 2 Pin Configuration ispLSI 2064VE 44-Pin TQFP Pinout Diagram I/O 28 I/O 29 I/O ...
Page 15
Part Number Description ispLSI 2064VE XXX X XXXX Device Family Device Number Speed f 280 = 280 MHz max* f 200 = 200 MHz max f 135 = 135 MHz max f 100 = 100 MHz max *Advanced Information ispLSI ...