HT82V46 HOLTEK [Holtek Semiconductor Inc], HT82V46 Datasheet - Page 13

• Manufacturer Part Number: HT82V46
• Description: 16-Bit, 45MSPS, 3-Channel CCD/CIS Analog Signal Processor
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

Reset Level Clamping (RLC)
There are Pixel-Clamping and Line-Clamping two
operating modes of HT82V46. It can be selected by
register bit CLPCTL. The clamp switch controlled
by an internal CLP signal, and must set the RLCEN
(default=1) register bit to 1 to enable clamping.
Pixel-clamping (CLPCTL=0)
• When WS=0 (Normal Mode) and CDS=X (both
• When WS=1 and CDS=1 (CDS mode only)
Rev. 1.10
for CDS mode and non-CDS mode).
The RLC switch is closed whenever the CDS1
input pin is high, as shown in Figure 10.
Reset Level Clamping in “WS” mode is only
possible in CDS mode and the time at which the
clamp switch is closed is concurrent with the
reference sample period, C1
11. RLC can be enabled on a pixel by pixel basis
under control of the CDS1 input pin. If CDS1 is
high when CDS2 is high and is sampled by ADCK
then clamping will be enabled for that input sample
at the time determined by CDSREF[1:0]. If CDS1
Analog
ADCK
CDS2
CDS1
Input
CLP
CLP
CLP
CLP
CLP
C1
C1
C1
C1
S
S
S
S
CDS2
CDS1
ADCK
CDSREF[1:0] = 00
CDSREF[1:0] = 01
CDSREF[1:0] = 10
CDSREF[1:0] = 11
CDSREF[1:0] = 00
CDSREF[1:0] = 01
CDSREF[1:0] = 10
CDSREF[1:0] = 11
C2
Figure 10 Pixel-Clamping RLC Operation, with CDS (Non-CDS also Possible)
S
C2
S
: Video Sample; C1
Figure 11 “WS” Mode (WS=1) RLC and Sampling
S
, as shown in Figure
S
: Reference Sample
13
Line-clamping (CLPCTL=1)
RLC switch closed when CDS1 = 1
• WS=0 (Normal Mode) and CDS=0 (Non-CDS
mode) only.
is low at this point then the RLC switch will not be
closed for that input sample. If RLC is required on
every pixel then the CDS1 pin can be constantly
held high in “WS” mode.
In situations where the input video signal does not
have a stable reference level it may be necessary
to clamp only during those pixels which have a
known state (e.g. the Dummy, or Black pixels at
the start or end of a line of most image sensors).
This is known as line-clamping and relies on
the input capacitor to hold the DC level between
clamp intervals. In non-CDS mode (CDS=0) this
can be done directly by controlling the CDS1
input pin to go high during the black pixels only.
Alternatively it is possible to use CDS1 to identify
the black pixels and enable the clamp at the same
time as the input is being sampled (i.e. when CDS2
is high and CDS1 is high). This mode is enabled
by setting CLPCTL=1 and the operation is shown
in Figure 12.
November 24, 2011
HT82V46