HT82V46 HOLTEK [Holtek Semiconductor Inc], HT82V46 Datasheet - Page 8

• Manufacturer Part Number: HT82V46
• Description: 16-Bit, 45MSPS, 3-Channel CCD/CIS Analog Signal Processor
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

Analog Input Signal Sampling
There are “NM” and “WS” two operating modes of
HT82V46. It can be selected by register bit WS.
“NM” Mode (WS=0; Normal Mode)
The ADCK speed can be specified along with the
ADCK:CDS2 ratio to achieve the desired sample rate
as table 1.
“NM” Mode Timing Diagram
See Figure 2 , Figure 3 and Figure 4.
“WS” Mode (WS=1)
It requires double rate ADCK and pixel rate CDS2
input. CDS1 pin performs same function as RLC/
ACYC pin.
ADCK: 45MHz; CDS: available
Rev. 1.10
Where X
ADCK:CDS2
(R, G, B)
3:1
2:1
1:1
―
―
OD[7:0]
Analog
ADCK
CDS1
CDS2
Input
1
: Disable; V
HB : High Byte; LB : Low Byte
n-4
HB
B
t ADH
Max. Sample
Rate (MSPS)
LB
B
1
22.5
15
45
―
―
: Enable
t ADFC1R
Pixel n
HB
R
t C1FC2R
LB
R
t ADL
Figure 2 3-channel CDS Analog Input Timing
HB
G
1CH
n-3
0
0
1
1
1
LB
G
Table 1 “NM” Operating Modes
t
ADFC2R
t ADC
HB
B
Register Bit
2CH
LB
B
0
1
0
0
1
HB
Pixel n+1
R
t C1
8
LB
R
CH[1:0]
XX
XX
XX
A programmable detect circuit allows the sampling
point derived from CDS2 pin. When set C2DET to
1, the circuit detects either a rising or falling edge
(determined by C2POS control bit) on the CDS2 input
pin and generates an internal INTC2 pulse. When
C2POS=1, a positive edge transition is detected and
when C2POS=0, a falling edge transition is detected.
INTC2 can optionally be delayed by a number of
ADCK periods, specified by the C2DLY[2:0] bits.
Figure 5 shows the sampling point occurs on the first
rising ADCK edge after this internal CDS2 pulse.
“WS” Mode Timing Diagram
See Figure 6 , Figure 7, Figure 8 and Figure 9.
00
01
10
11
HB
G
n-2
LB
G
t C2
HB
t C2FADR
t
B
OD
Red
V
V
V
X
X
―
―
1
1
1
1
1
LB
B
R/G/B of PGA
HB
R
Pixel n+2
Green
t
OD
LB
R
V
V
X
V
X
―
―
1
1
1
1
1
HB
G
t PR3
n-1
LB
G
November 24, 2011
Blue
V
X
X
X
V
―
―
HB
1
1
1
1
1
B
HT82V46
LB
B
3-channel
2-channel
1-channel
Invalid
Invalid
Mode
HB
R