HT82V46 HOLTEK [Holtek Semiconductor Inc], HT82V46 Datasheet - Page 21

• Manufacturer Part Number: HT82V46
• Description: 16-Bit, 45MSPS, 3-Channel CCD/CIS Analog Signal Processor
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

Rev. 1.10
register 4
register 5
Register
Setup
Setup
Bit No.
3:2
7:4
0
1
0
1
2
3
4
5
6
7
Reserved
CDACPD
Reserved
INTM[1:0
LNBYLN
GRNPD
REDPD
ADCPD
CMLPD
BLUPD
REFPD
Name
ACYC
POR.
0000
00
0
0
0
0
0
0
0
0
0
0
Selects line by line operation. Line by line operation is intended for use
with systems which operate one line at a time but with up to three color
shared on the one output.
If LNBYLN=0 then ACYC bit no effect.
ACYC bit determines CDS1 pin and offset/gain register controls
When LNBYLN=0 or ACYC=1 this bit has no effect.
When LNBYLN=1 and ACYC=0.
Controls the offset/gain mux selector.
When set powers down red S/H, PGA
When set powers down green S/H, PGA
When set powers down blue S/H, PGA
When set powers down ADC, allows reduced power consumption
without powering down the references which have a long time constant
when switching on/off due to the external decoupling capacitors.
When set powers down 4-bit RLCDAC, setting the output to a high
impedance state and allowing an external reference to be driven in on
the VRLC/VBIAS pin.
When set disables REFT, REFB buffers to allow external references to
be used.
When set disable CML buffer to allow an externa reference to be used.
Must be set to 0
0= CDS1 pin is for Reference Sampling or Reset Level Clamp
1= Auto-cycling enabled by pulsing CDS1 pin and input signal
00= Red offset/gain registers applied to input channel.
01= Green offset/gain registers applied to input channel.
10= Blue offset/gain registers applied to input channel.
11= Reserved.
control. And INTM[1:0] bits are for gain/offset multiplexers control.
switched to next gain/offset register sequentially. And sequence is
Red -> Green -> Blue -> Red etc. At this mode, it must set
CDS=0 and use CLPCTL bit instead CDS1 pin to control RLC.
21
Description
November 24, 2011
HT82V46