ISPLSI2128V-60LJ84 LATTICE [Lattice Semiconductor], ISPLSI2128V-60LJ84 Datasheet

ISPLSI2128V-60LJ84

Manufacturer Part Number

ISPLSI2128V-60LJ84

Description

3.3V High Density Programmable Logic

Manufacturer

LATTICE [Lattice Semiconductor]

Datasheet

1.ISPLSI2128V-60LJ84.pdf (15 pages)

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LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

• HIGH DENSITY PROGRAMMABLE LOGIC

• 3.3V LOW VOLTAGE 2128 ARCHITECTURE

• HIGH PERFORMANCE E

• IN-SYSTEM PROGRAMMABLE

• THE EASE OF USE AND FAST SYSTEM SPEED OF

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

2128v_14

Features

— 6000 PLD Gates

— 128 and 64 I/O Pin Versions, Eight Dedicated Inputs

— 128 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

— Small Logic Block Size for Random Logic

— Interfaces with Standard 5V TTL Devices

— The 128 I/O Pin Version is Fuse Map Compatible

—

— Electrically Erasable and Reprogrammable

— Non-Volatile

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

— 3.3V In-System Programmability (ISP™) Using

— Open-Drain Output Option for Flexible Bus Interface

— Increased Manufacturing Yields, Reduced Time-to-

— Reprogram Soldered Devices for Faster Prototyping

PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

— PC and UNIX Platforms

Machines, Address Decoders, etc.

with 5V ispLSI 2128

Boundary Scan Test Access Port (TAP)

Capability, Allowing Easy Implementation of

Wired-OR or Bus Arbitration Logic

Market and Improved Product Quality

Interconnectivity

Tools, Timing Simulator and ispANALYZER™

max = 80 MHz Maximum Operating Frequency

pd = 10 ns Propagation Delay

CMOS

TECHNOLOGY

The ispLSI 2128V is a High Density Programmable Logic

Device available in 128 and 64 I/O-pin versions. The

device contains 128 Registers, eight Dedicated Input

pins, three Dedicated Clock Input pins, two dedicated

Global OE input pins and a Global Routing Pool (GRP).

The GRP provides complete interconnectivity between

all of these elements. The ispLSI 2128V features in-

system programmability through the Boundary Scan

Test Access Port (TAP). The ispLSI 2128V offers non-

volatile reprogrammability of the logic, as well as the

interconnect to provide truly reconfigurable systems.

The basic unit of logic on the ispLSI 2128V device is the

Generic Logic Block (GLB). The GLBs are labeled A0, A1

.. D7 (see Figure 1). There are a total of 32 GLBs in the

ispLSI 2128V device. Each GLB is made up of four

macrocells. Each GLB has 18 inputs, a programmable

AND/OR/Exclusive OR array, and four outputs which can

be configured to be either combinatorial or registered.

Inputs to the GLB come from the GRP and dedicated

inputs. All of the GLB outputs are brought back into the

GRP so that they can be connected to the inputs of any

GLB on the device.

Functional Block Diagram*

Description

*128 I/O Version Shown

3.3V High Density Programmable Logic

Output Routing Pool (ORP)

Global Routing Pool (GRP)

ispLSI

Logic

Array

Output Routing Pool (ORP)

September 2000

2128V

GLB

0139A/2128V

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ISPLSI2128V-60LJ84 Summary of contents

Page 1

Features • HIGH DENSITY PROGRAMMABLE LOGIC — 6000 PLD Gates — 128 and 64 I/O Pin Versions, Eight Dedicated Inputs — 128 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. ...

Page 2

Functional Block Diagram Figure 1. ispLSI 2128V Functional Block Diagram (128-I/O and 64-I/O Versions) RESET Input Bus GOE 0 GOE 1 Output Routing Pool (ORP) Output Routing Pool (ORP) Megablock I I/O 1 ...

Page 3

Absolute Maximum Ratings Supply Voltage V .................................. -0.5 to +5.6V cc Input Voltage Applied ............................... -0.5 to +5.6V Off-State Output Voltage Applied ............ -0.5 to +5.6V Storage Temperature ................................ -65 to 150 C Case Temp. with Power Applied .............. -55 ...

Page 4

Switching Test Conditions Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. Output Load Conditions (see Figure 2) TEST CONDITION A 316 ...

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ISPLSI2128V-60LJ84 LATTICE [Lattice Semiconductor], ISPLSI2128V-60LJ84 Datasheet

ISPLSI2128V-60LJ84

Related parts for ISPLSI2128V-60LJ84

ISPLSI2128V-60LJ84 Summary of contents

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