F25L08PA-100DG ESMT [Elite Semiconductor Memory Technology Inc.], F25L08PA-100DG Datasheet - Page 17

• Manufacturer Part Number: F25L08PA-100DG
• Description: 3V Only 8 Mbit Serial Flash Memory with Dual
• Manufacturer: ESMT [Elite Semiconductor Memory Technology Inc.]

ESMT
Write Enable (WREN)
The Write Enable (WREN) instruction sets the Write-Enable-
Latch bit in the Software Status Register to 1 allowing Write
operations to occur.
The WREN instruction must be executed prior to any Write
Write Disable (WRDI)
The Write Disable (WRDI) instruction resets the Write-Enable-
Latch bit to 0 disabling any new Write operations from occurring
or exits from OTP mode to normal mode.
Enable Write Status Register (EWSR)
The Enable Write Status Register (EWSR) instruction arms the
Write Status Register (WRSR) instruction and opens the status
register for alteration. The Enable Write Status Register
instruction does not have any effect and will be wasted, if it is not
followed immediately by the Write Status Register (WRSR)
Elite Semiconductor Memory Technology Inc.
Figure 17: Write Enable (WREN) Sequence
Figure 18: Write Disable (WRDI) Sequence
SCK
SO
CE
SI
SCK
SO
CE
SI
MODE0
MODE3
MODE0
MODE3
MSB
HIGH IMPENANCE
MSB
0 1 2 3 4 5 6 7
HIGH IMPENANCE
0 1 2 3 4 5 6 7
06
(Program/Erase) operation. CE must be driven high before the
WREN instruction is executed.
executed.
instruction. CE must be driven low before the EWSR instruction
is entered and must be driven high before the EWSR instruction
is executed.
CE must be driven high before the WRDI instruction is
04
Publication
Revision: 1.7
F25L08PA
Date: Jul. 2009
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