AT83C24 ATMEL Corporation, AT83C24 Datasheet - Page 14

• Manufacturer Part Number: AT83C24
• Description: Smart Card Reader Interface with Power Management
• Manufacturer: ATMEL Corporation

Activation Sequence
Hardware Activation (DC/DC started with CMDVCC)
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AT83C24
Initial conditions:
CARDDET bit must be configured in accordance to the smart card connector polarity.
IT_SEL bit, CRST_SEL bit (see CONFIG4 register) must be set and CARDRST bit (see
INTERFACE register) must be cleared. A smart card must be detected to enable to start
the DC/DC (CVCC= 3V or 5V).
The hardware activation sequence is started by hardware with CMDVCC pin going high
to low. It follows this automatic sequence:
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•
•
•
Note:
Note:
Figure 10. Activation sequence with CMDVCC
CIO / CC4 / CC8 and IO / C4 / C8 are respectively linked together (IODIS bit is
cleared).
The DC/DC is started and CVCC is set according to the A0/3V pin: 5V (Class A) if
A0/3V is High and 3V (Class B) is A0/3V is Low.
CCLK signal is enabled (CKSTOP bit cleared) when CVCC has settled to the
programmed voltage (see Electrical Characteristics) and the level on A1/RST is 0.
The CCLK source can be DCCLK signal, CLK signal , A2/CK signals or CARDCK bit
(see Figures 5).
CRST signal is linked with A1/RST pin as soon as A1/RST pin level is 0. A rising
edge on A1/RST pin set the CRST pin.
1. The card must be deactivated to change the voltage.
For NDS applications, the host usually starts activation with A1/RST = 0.
CMDVCC
A1/RST
CCLK
CVCC
CRST
CIO
4234E–SCR–09/04