AT83C24 ATMEL Corporation, AT83C24 Datasheet - Page 9

• Manufacturer Part Number: AT83C24
• Description: Smart Card Reader Interface with Power Management
• Manufacturer: ATMEL Corporation

Read Command
Interrupts
4234E–SCR–09/04
After the slave address has been configured, the read command allows to read one or
several bytes in the following order:
•
•
Note:
Table 4. Read Command Description
The PRES/INT behavior depends on IT_SEL bit value (see CONFIG4 register).
•
STATUS, CONFIG0, CONFIG1, CONFIG2, CONFIG3, INTERFACE, TIMER1,
TIMER0, CAPTURE1, CAPTURE0
FFh is completing the transfer if the microcontroller attempts to read beyond the last
byte.
If IT_SEL= 0, the PRES/INT output is High by default (on chip pull up or open drain).
PRES/INT is driven Low by any of the following event:
–
–
–
–
–
If IT_SEL=0, a read command of STATUS register and of CONFIG0 register will
release PRES/INT pin to high level.
Several AT83C24 devices can share the same interrupt and the microcontroller can
identify the interrupt sources by polling the status of the AT83C24 devices using
TWI commands.
Flags are only reset after the corresponding byte read has been acknowledged by the
master.
INSERT bit set in CONFIG0 register (card insertion/extraction or bit set by
software )
VCARD_INT bit set in STATUS register (the DC/DC output voltage has
settled)
over-current detection on CVCC
VCARDERR bit set in CONFIG0 register (out of range voltage on CVCC or
bit set by software)
ATRERR bit set in CONFIG0 register (no ATR before the card clock counter
overflows or bit set by software).This control of ATR timing is only available if
ART bit =1.
Byte Description
Address byte
Data byte 10
Data byte 12
Data byte 11
Data byte 1
Data byte 2
Data byte 3
Data byte 4
Data byte 5
Data byte 6
Data byte 7
Data byte 8
Data byte 9
CAPTURE 1 (MSB)
CAPTURE 0 (LSB)
TIMER 1 (MSB)
TIMER 0 (LSB)
0100 A
INTERFACE
Byte Value
CONFIG0
CONFIG1
CONFIG2
CONFIG3
CONFIG4
STATUS
0xFF
2
A
1
A
0
AT83C24
1
9