SAF82525 Infineon Technologies AG, SAF82525 Datasheet - Page 101
SAF82525
Manufacturer Part Number
SAF82525
Description
Data Communications ICs
Manufacturer
Infineon Technologies AG
Datasheet
1.SAF82525.pdf
(126 pages)
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Semiconductor Group
CIE … Clear To Send Interrupt Enable
RIE … Receive Frame Start Interrupt Enable
DIV … Data Inversion
XCS0, RCS0 … Transmit/Receive Clock Shift, Bit 0
Any state transition at the CTS input pin may cause an interrupt which is indicated in the
EXIR register (CSC bit). The actual state at the CTS pin can be determined reading the CTS
bit of the STAR register.
0 … disable
1 … enable
When, the RFS interrupt (via EXIR) is enabled!
Only valid if NRZ data encoding is selected. Data is transmitted and received inverted.
Together with bits XCS2, XCS1 (RCS2, RCS1) in TSAX (TSAR) the clock shift relative to
the frame synchronization signal of the transmit (receive) time-slot can be adjusted.
A clock shift of 0 … 7 bits is programmable (clock mode 5 only!).
101
SAB 82525
SAB 82526
SAF 82525
SAF 82526