SAF82525 Infineon Technologies AG, SAF82525 Datasheet - Page 48

• Manufacturer Part Number: SAF82525
• Description: Data Communications ICs
• Manufacturer: Infineon Technologies AG

If frames longer than 64 bytes are received, the device will repeatedly prompt to read out 32-
byte data blocks via interrupt or DMA.
In the case of several shorter frames, up to 17 may be stored in the HSCX.
If the accessible half of the RFIFO contains a frame i (or the last part of frame i), up to 16 short
frames may be stored in the other half (i + 1,. . ., i + n) meanwhile, prior to frame i being fetched
from the RFIFO.
This is illustrated in figure 22.
For a description of a transmit and receive sequence in both Interrupt or DMA Mode, please
refer to chapter 7.2 and 7.3.
Figure 22
Configuration of RFIFO (Short Frames)
Note: The number of 17 frames applies e.g. for the HSCX operating in the auto or non-auto
Semiconductor Group
mode (address recognition), and short frames only containing the HDLC Address and
Control field are received. Since the address is not stored, the control field is always
stored first in the RFIFO, and an additional status byte is always appended at the end
of each frame in the RFIFO, these frames will occupy two bytes.
32
Inaccessible
32
Accessible
Bytes
Bytes
a) Prior to
Acknowledgement
Frame
Frame
Last Part
of Frame
i + n
i + 1
i
48
0
<
n
<
_
16
b) After
Acknowledgement
Frame i + 1
Frame i + n
Frame i + 2
ITD00486
SAB 82525
SAB 82526
SAF 82525
SAF 82526