DS89C430-DS89C450 Dallas Semiconducotr, DS89C430-DS89C450 Datasheet - Page 30

• Manufacturer Part Number: DS89C430-DS89C450
• Description: Ultra-High-Speed Flash Microcontrollers
• Manufacturer: Dallas Semiconducotr

Figure 10. Page Mode 1, External Memory Cycle (CD1:CD0 = 10)
During a page miss, P2 drives the Addr [8:15] of the 16-bit address and holds it for the duration of the first half of
the memory cycle to allow the external address latches to latch the new most significant address byte. ALE is
asserted to strobe the external address latches. During this operation, PSEN , RD , and WR are held in inactive
states and P0 is in a high-impedance state. The following half-memory cycle is executed as a page hit cycle and
the appropriate operation takes place.
A page miss can occur at set intervals or during external operations that require a memory access into a page of
memory that has not been accessed during the last external cycle. Generally, the first external memory access
causes a page miss. The new page address is stored internally and is used to detect a page miss for the current
external memory cycle.
Internal Memory Cycles
XTAL1
Port 0
Port 2
RD/WR
Port 0
Port 2
RD/WR
RD/WR
PSEN
Port 2
Port 0
ALE
PSEN
ALE
PSEN
ALE
MSB
Page Miss
MSBAdd
LSB
Page Miss
Inst
MSBAdd
LSB
Inst
Page Hit
LSB Add
LSB
MOVX
External Memory Cycles
Page Miss
MOVX MOVX
LSB
MOVX executed
Page Hit
30 of 47
LSB Add
MSB
Data Access
Inst
MOVX executed
LSB Add
LSB
Data
MSBAdd
Inst
MSB
Page Miss
Data Access
MOVX executed
LSB
Inst
LSB Add
Data Access
MSB
Data
Data Access
LSB Add
LSB
next instruction
Data
Page Miss
MSBAdd
Data
MSB
PAGES=00
PAGES=01
PAGES=10