DS5001FP-12-44 Dallas Semiconducotr, DS5001FP-12-44 Datasheet

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... VCC0 12 VCC 13 MSEL 14 P1.0 15 BA14 16 P1.1 17 BA12 18 P1.2 19 BA7 20 P1.3 21 PE3 22 PE4 23 BA6 80-Pin MQFP 44-Pin MQFP DS5001FP 64 P2.6/A14 63 CE3 62 CE4 61 BD3 60 P2.5/A13 59 BD2 58 P2.4/A12 57 BD1 56 P2.3/A11 55 BD0 54 VLI 53 BA15 52 GND 51 P2.2/A10 50 P2 ...

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... Refer to the Secure Microcontroller User’s Guide for operating details. This data sheet provides ordering information, pinout, and electrical specifications. ORDERING INFORMATION PART PIN-PACKAGE DS5001FP-16 80-MQFP DS5001FP-16N 80-MQFP DS5001FP-12-44 44-MQFP MAX. CLOCK SPEED (MHz DS5001FP TEMP. RANGE (°C) ...

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... Figure 1. BLOCK DIAGRAM DS5001FP ...

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... At this time, PSEN down externally. This should only be done once the DS5001FP is already in a reset state. The device that pulls down should be open drain since it must not interfere with under normal operation. Active-High Reset Input. A logic 1 applied to this pin will activate a reset state. This pin is pulled down internally so this pin can be left unconnected if not used ...

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... This I/O pin (open drain with internal pullup) indicates that the power supply (V has fallen below the V 42 N/A DS5001FP drives this pin to a logic 0. Because the micro is lithium-backed, this signal is VRST guaranteed even when V low externally. This allows multiple parts to synchronize their power-down resets. ...

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... SRAM, a lithium cell, and a real-time clock. This is packaged in a 72-pin SIMM module. MEMORY ORGANIZATION Figure 2 illustrates the memory map accessed by the DS5001FP. The entire 64k of program and 64k of data are potentially available to the byte-wide bus. This preserves the I/O ports for application use. The user controls the portion of memory that is actually mapped to the byte-wide bus by selecting the program range and data range ...

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... Figure 3. MEMORY MAP IN PARTITIONABLE MODE ( Note: Partitionable mode is not supported when MSEL pin = 0 (128kB mode DS5001FP ...

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... Figure 4. MEMORY MAP WITH PES = DS5001FP ...

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... RAM chip Figure 6 shows a similar system with using two 32kB SRAMs. The byte-wide address bus connects to the SRAM address lines. The bidirectional byte-wide data bus connects the data I/O lines of the SRAM. Figure 5. CONNECTION TO 128k x 8 SRAM DS5001FP ...

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... Low power SRAMs should be used for this reason. When using the DS5001FP, the user must select the appropriate battery to match the RAM data retention current and the desired backup lifetime. Note that the lithium cell is only loaded when V more information on this topic ...

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... IH2 V OL1 ) PF , PSEN V OL2 , V 2.4 OH1 , PSEN V 2.4 OH2 , 0.5V and V = 0V. In this 0°C to +70° ±10%) CC TYP MAX UNITS + 0.15 0.45 V 0.15 0.45 V 4.8 V 4.8 V -50 µA -500 µA -600 µA DS5001FP NOTES ...

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... ±10%) CC TYP MAX UNITS +10 µA 150 kW 180 kW 4 4.37 4.50 V 4.37 4.6 V 4.12 4.25 V 4.09 4. 7 µ 500 nA 4.25 4.25 4.65 DS5001FP NOTES ...

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... CLK 9t - 165 CLK 9t - 105 CLK CLK CLK 4t - 130 CLK CLK 7t - 150 CLK CLK CLK CLK CLK DS5001FP UNITS MHz ...

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... EXPANDED PROGRAM-MEMORY READ CYCLE EXPANDED DATA-MEMORY READ CYCLE DS5001FP ...

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... EXPANDED DATA-MEMORY WRITE CYCLE DS5001FP ...

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... External Clock-Low Time 29 External Clock-Rise Time 30 External Clock-Fall Time 31 EXTERNAL CLOCK TIMING (T = 0°C to +70° SYMBOL MIN at 12MHz t CLKHPW at 16MHz at 12MHz t CLKLPW at 16MHz at 12MHz t CLKR at 16MHz at 12MHz t CLKF at 16MHz DS5001FP = 5V ±10%) CC MAX UNITS ...

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... AC CHARACTERISTICS (continued) POWER CYCLE TIME # PARAMETER 32 Slew Rate from V CCMIN 33 Crystal Startup Time 34 Power-On Reset Delay POWER CYCLE TIMING (T = 0°C to +70° SYMBOL CSU t POR DS5001FP = 5V ±10%) CC MIN MAX UNITS 130 µs (Note 9) 21,504 t CLK ...

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... Clock-Rising Edge to Input-Data Valid 39 Input-Data Hold After Rising-Clock Edge SERIAL PORT TIMING, MODE 0°C to +70° SYMBOL MIN t 12t SPCLK CLK t 10t - 133 DOCH CLK 117 CHDO CLK t CHDV t 0 CHDIV DS5001FP = 5V ±10%) CC MAX UNITS µ 10t - 133 CLK ns ...

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... RWHDV t Low Time) W RWLPW 0°C to +70° ±10%) CC MIN MAX CEPW CLK CLK CLK CLK CLK CLK CLK CLK CLK DS5001FP UNITS ...

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... Hold After Pulse Width Data-Out Delay Data-Out Delay Data-Float Delay RD = 0°C to +70° SYMBOL MIN 160 RDZ DS5001FP = 5V ±10%) CC MAX UNITS 130 ns 130 ...

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... 0°C to +70° SYMBOL t ACC t CAC t ACD t CRQ (T = 0°C to +70°C; V PROG A SYMBOL t PRA t PRI DS5001FP = 5V ±10%) CC MIN MAX UNITS 160 ns 130 ±10%) CC MIN MAX UNITS 130 ...

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... RPC TIMING MODE DS5001FP ...

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... This parameter applies to industrial temperature operation. 11) pin operation is specified with input when and < and a maximum load of 10µ ³ 3.0V. BAT MSEL = RST = MSEL = XTAL2 not CC = +25° normal operation. CCO is disconnected. CCO . CCO DS5001FP , CLKR , CLKR ...

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... MQFP MM DIM MIN MAX A - 3. 2.55 2.87 B 0.30 0.50 C 0.13 0.23 D 23.70 24.10 D1 19.90 20.10 E 17.70 18.10 E1 13.90 14.10 e 0.80 BSC L 0.65 0.95 56-G4005-001 DS5001FP ...

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... MQFP DS5001FP ...

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... PFW 5) Added industrial specification for I 6) Reduced t and t CE1HOV CEHDV The following represent the key differences between 051099 and 052499 version of the DS5001FP data sheet. Please review this summary carefully. 1) Minor markups and ready for approval 0.65 (PCN F62501 ...