IS42S16100 Integrated Silicon Solution, IS42S16100 Datasheet - Page 7

• Manufacturer Part Number: IS42S16100
• Description: 512K Words x 16Bits x 2 Banks Synchronous Dynamic RAM
• Manufacturer: Integrated Silicon Solution

IS42S16100
OPERATING FREQUENCY / LATENCY RELATIONSHIPS
AC TEST CONDITIONS
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
11/01/01
Input
Output Load
SYMBOL
—
—
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CAC
RCD
RAC
RC
RAS
RP
RRD
CCD
DPL
DAL
RBD
WBD
RQL
WDL
PQL
QMD
DMD
MCD
PARAMETER
Clock Cycle Time
Operating Frequency
CAS Latency
Active Command To Read/Write Command Delay Time
RAS Latency (t
Command Period (REF to REF / ACT to ACT)
Command Period (ACT to PRE)
Command Period (PRE to ACT)
Command Period (ACT[0] to ACT [1])
Column Command Delay Time
(READ, READA, WRIT, WRITA)
Input Data To Precharge Command Delay Time
Input Data To Active/Refresh Command Delay Time
(During Auto-Precharge)
Burst Stop Command To Output in HIGH-Z Delay Time
(Read)
Burst Stop Command To Input in Invalid Delay Time
(Write)
Precharge Command To Output in HIGH-Z Delay Time
(Read)
Precharge Command To Input in Invalid Delay Time
(Write)
Last Output To Auto-Precharge Start Time (Read)
DQM To Output Delay Time (Read)
DQM To Input Delay Time (Write)
Mode Register Set To Command Delay Time
OUTPUT
INPUT
CLK
(Input/Output Reference Level: 1.4V)
RCD
I/O
2.8V
1.4V
0.0V
2.8V
1.4V
0.0V
+ t
CAC
t
OH
)
t
CS
50 pF
1.4V
t
CH
t
CHI
t
50 Ω
AC
t
CK
t
CL
1.4V
+1.4V
166
–2
-6
6
3
3
6
9
6
3
3
1
1
4
3
0
3
0
2
0
2
143
–1
-7
7
3
3
6
9
6
3
3
1
1
4
3
0
3
0
2
0
2
-10.
100
10
–1
9
3
4
0
3
0
2
3
3
6
6
3
1
1
3
0
2
ISSI
UNITS
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
MHz
ns
®
7